ThIs product is covered under multiple patents held or licensed by Comtech AHA
Corporation.
This product is covered by a Turbo Code Patent License from France Telecom -
TDF - Groupe des ecoles des telecommunications.
comtech aha corporation
comtech aha corporation
PRODUCT BRIEF
AHA4524
(4 Kbit Block Version)
TURBO PRODUCT CODE ENCODER/DECODER
The AHA4524 device is a single-chip Turbo
Product Code (TPC) Forward Error Correction
(FEC) Encoder/Decoder. This device integrates
independent TPC encoder and decoder functions,
and can be configured for full or half duplex
operation. In addition to TPC coding, the device
includes helical interleaving, CRC computation,
and data scrambling. Each of the functional blocks
can be independently bypassed. Figure 1 shows the
functional block diagram.
The encoder and decoder accept data and
configuration through a synchronous 3-wire or data
bus interface designed to connect directly to a DSP
or user logic.
Encoder and decoder configuration registers are
written and read through the same interface as the
data. Configuration registers may be accessed at the
start of every block transfer.
The encode datapath, with all functional blocks
enabled, computes and inserts CRC bits, scrambles
the data, inserts error correction code (ECC) bits,
and helically interleaves the data. The decoder
datapath is the reverse of the encoder datapath. With
all functional blocks enabled, the received data is
helically deinterleaved before decoding. The
decoder output is descrambled, and the CRC is
computed to verify data integrity. Decoded data is
then output in a serial bit stream.
The decoder input interface includes an option to
accept 4 bit parallel soft metric data symbols. The
parallel decoder input is used to support a symbol per
transfer for fast channel input rates. The AHA4524
also includes fast code changing feature which
allows the device to process multiple block types
simultaneously.
FEATURES
PERFORMANCE:
• 60 Mbit/sec channel rate and 50 Mbit/sec payload
data rate for (64,57)x(64,57) code with 3
iterations
• Integrated 16 bit scrambler and descrambler
• Integrated 32 bit CRC computation and
verification
• Supports two dimensional (2D) and three
dimensional (3D) Turbo Product Codes
• Supports 2D enhanced Turbo Product Codes
• Correction count for channel SNR estimation
• Simultaneously processes multiple block types
FLEXIBILITY:
• Code Rates from 0.25 to 0.97
• Encoded block Sizes from 64 bits to 4 Kbits
• Programmable code shortening supports exact
block sizes
• Programmable decoder input quantization for up
to 4 bit wide soft metrics
• Programmable iterations up to 255 per block
• 4 programmable block configurations which are
selectable for fast code changing
• On chip PLL allows low frequency system clock
CHANNEL INTERFACE:
• Synchronous 3-wire input and output ports
designed to be compatible with DSP serial ports
• Bus mode input and output ports designed to be
compatible with a DSP bus
• Chip selects on encoder and decoder ports for full
or half-duplex operation
• Pin selectable interface control signal polarity
• Decoder supports 4 bit parallel soft metric input
data for fast decode operation
SYSTEM INTERFACE:
• Secondary input communication cycles are used
for accessing the AHA4524 configuration
registers through the data ports
• Block status is optionally output at the end of
every decoded block to provide correction and
CRC error information
ELECTRICAL:
• 3.3V I/O, 1.8V core operation
• 5V tolerant inputs
• TTL signal compatible
• 64 pin TQFP Package
• Commercial or Industrial temperature rating
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