 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PCA6107 Datasheet(PDF) 5 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
PCA6107 Datasheet(HTML) 5 Page - Texas Instruments |
|
|
5 / 24 page 
www.ti.com D FF Q D Q FF D Q FF D Q FF Data From Shift Register Data From Shift Register Write Configuration Pulse Write Pulse Read Pulse Data From Shift Register Write Polarity Pulse CK Q CK Q CK Q CK Q Polarity Inversion Register Input Port Register Output Port Register Configuration Register VCC GND Input Port Register Data Polarity Register Data ESD Protection Diode P1 to P7 Output Port Register Data I2C Interface PCA6107 REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006 SIMPLIFIED SCHEMATIC OF P1 TO P7 A. On power up or reset, all registers return to default values. The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. I2C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on the SDA input/output while the SCL input is high (see Figure 1). After the Start condition, the device address byte is sent, MSB first, including the data direction bit (R/W). After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input/output during the high of the ACK-related clock pulse. The address inputs (A0–A2) of the slave device must not be changed between the Start and the Stop conditions. On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control commands (Start or Stop) (see Figure 2). A Stop condition, a low-to-high transition on the SDA input/output while the SCL input is high, is sent by the master (see Figure 1). Any number of data bytes can be transferred from the transmitter to the receiver between the Start and the Stop conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure 3). When a slave receiver is addressed, it must generate an ACK after each byte is received. Similarly, the master must generate an ACK after each byte that it receives from the slave transmitter. Setup and hold times must be met to ensure proper operation. 5 Submit Documentation Feedback |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
