OV-0004 May 06

External—Free Release

Page 6 of 11

OXCFU950 OVERVIEW

OXFORD SEMICONDUCTOR, INC.

Pin Number

Pin Name

Description

55

I_C_33_5_N_

DSR#

Active-low modem data-set-ready input. If automated DSR# flow control

is enabled, upon de-assertion of the DSR# pin, the transmitter completes

the current character & enters idle mode until the DSR# pin is

reasserted. Note: flow control characters are transmitted regardless of

the state of the DSR# pin.

57

I_C_33_5_N_

RI#

Active-low modem ring-indicator input.

1

P_33

UART_VDD3V3

Power supply to UART and MIO I/O interfaces. Voltage on these pins

should be tied to 1.8 V to 3.3 V supply (depending on requirement).

51

A_18

XTLO

Crystal oscillator output.

50

A_18

XTLI

Crystal oscillator input. Frequency = 12 MHz.

Note : a pull-down resistor of 500 K

Ω is required on this pin.

49

P_18

PLL_VSS1V8

Ground (0 Volts) for PLL & oscillator cells. This pin should be tied to

ground.

48

P_18

PLL_VDD1V8

Power supply for PLL & oscillator cells. This pin should be tied to 1.8

volts (i.e. tied to REG_VDD1V8 pin).

2

A_33

USB_DP

USB data plus.

3

A_33

USB_DM

USB data minus.

4

P_33

USB_VDD3V3

Power supply to USB I/O interface. This pin should be tied to 3.3 volts.

64,63,62,61

B_T_33_5_N_1_

MIO[3:0]

Multipurpose IO pins.

Note: if enabled, MIO[3:0] can be used as an interrupt inputs.

MIO[3:2] can be configured to act as the USB power management

control signals PORT_OVER_CURRENT & PORT_POWER

52

I_C_33_5_N_U

CIS_MODE

Test mode select pin/default CIS select

20

I_C_33_5_N_D

TEST

Test pin. This pin should be tied to VSS for normal operation.

Additional Power and Ground

65 (Thermal bonding

pad)

P_00

VSS

Main digital ground pin. The VSS pin should be tied to ground. Note this

is the thermal bonding pin underneath the 64-pin QFN package

27

P_18

REG_VDD1V8

Output supply from internal voltage regulator at 1.8 V. Can be used as

power supply to PLL (i.e. pin #48).

Table 1: Pin Descriptions

Note 1 : Pad syntax description

Pad type

Syntax

Digital Input pad

t_a_xy_h_i_p

Digital Output pad

t_a_xy_d

Digital Tristate output pad

t_a_xy_d

Digital Bidirectional pad

t_a_xy_h_i_d_p

Analogue pad

t_xy

Power Pad

t_xy

Table 2: Pad Type Syntax