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OX16PCI954-TQC60-A Datasheet(PDF) 9 Page - Oxford Semiconductor |
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OX16PCI954-TQC60-A Datasheet(HTML) 9 Page - Oxford Semiconductor |
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9 / 72 page  Data Sheet Revision 1.3 Page 9 OX16PCI954 OXFORD SEMICONDUCTOR LTD. Mode 00 01 10 11 Dir1 Name Description Serial port pins 81, 78, 58, 53 N/A O RTS[3:0]# Active-low modem request-to-send output. If automated RTS# flow control is enabled, the RTS# pin is deasserted and reasserted whenever the receiver FIFO reaches or falls below the programmed thresholds, respectively. 83, 76, 60, 51 N/A I CTS[3:0]# Active-low modem clear-to-send input. If automated CTS# flow control is enabled, upon deassertion of the CTS# pin, the transmitter will complete the current character and enter the idle mode until the CTS# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the CTS# pin. 84, 75, 61, 50 N/A I I DSR[3:0]# Rx_Clk_In[3:0] Active-low modem data-set-ready input. If automated DSR# flow control is enabled, upon deassertion of the DSR# pin, the transmitter will complete the current character and enter the idle mode until the DSR# pin is reasserted. Note: flow control characters are transmitted regardless of the state of the DSR# pin External receiver clock for isochronous applications. The Rx_Clk_In is selected when CKS[1:0] = ‘01’. 86, 73, 67, 48 N/A I I RI[3:0]# Tx_Clk_In[3:0] Active-low modem Ring-Indicator input External transmitter clock. This clock can be used by the transmitter (and indirectly by the receiver) when CKS[6]=’1’. 64 N/A O XTLO Crystal oscillator output 63 N/A I XTLI Crystal oscillator input or external clock pin. Maximum frequency 60MHz 8-bit local bus 71 N/A O UART_Clk_Out Buffered crystal output. This clock can drive external UARTs connected to the local bus. Can be enabled / disabled by software. 122 N/A O LBRST Local bus active-high reset 123 N/A O LBRST# Local bus active-low reset 102 N/A O LBDOUT Local bus data out enable. This pin can be used by external transceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode. 109 N/A O LBCLK Buffered PCI clock. Can be enabled / disabled by software 114-7 N/A O O LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode) Local bus active-low Data-Strobe (Motorola mode) 112 N/A O O LBWR# LBRDWR# Local Bus active-low write-strobe (Intel mode) Local Bus Read-not-Write control (Motorola mode) 113 N/A O Z LBRD# Hi-Z Local Bus active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) 105-8 118-21 N/A O LBA[7:0] Local bus address signals 92-5 98-101 N/A See 32-bit Local bus I/O LBD[7:0] Local bus data signals |
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