ADAV400 datasheet(28/36 Pages) AD

Part #	ADAV400

Description	Audio Codec with Embedded SigmaDSP Processor

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ADAV400

Rev. 0 | Page 28 of 36

CONTROL REGISTERS

Table 28. Audio Register Map

Register Address (Hex)

Register Name

Register Width (Bits)

0x1052

Audio core control register (see Table 29)

16

0x1053

RAM modulo control register (see Table 30)

8

0x1054

Serial output control register (see Table 31)

16

0x1055

Serial input control register (see Table 32)

8

0x1056

SRC serial port control register (see Table 33)

8

0x1057

ADC input mux control register (see Table 34)

16

0x1058

Power control register (see Table 35)

16

0x1059

User Control Register 1 (see Table 37)

16

0x105A

User Control Register 2 (see Table 36)

16

0x110D

DAC amplifier register (see Table 38)

16

0x1113

Headphone amplifier register (see Table 39)

16

Table 29. Audio Core Control Register

Register Address 0x1052

Default Readback = 0x4000

Register Bits

Function

15

Reserved (set to 0)

141

Enable SDO2 and SDO3

0 = enabled

1 = disabled

13

Indicates when slew RAM is muted (read only)

12

Equivalent to writing 0s to the target RAM

0 = normal operation

1 = RAM zeroed

11

Reserved (set to 0)

10

Reserved (set to 0)

9

Clears internal processor registers (active low)

0 = registers cleared

1 = normal operation

8

Forces multiplier input to 0

0 = normal operation

1 = forced to 0

7

Initializes data RAM to zero

0 = normal operation

1 = enabled

Register Bits

Function

6

Mutes serial input ports

0 = normal operation

1 = muted

5

Initiates safeload-to-target/slew RAM

0 = off

1 = on

4

Initiates safeload-to-parameter RAM

0 = off

1 = on

3:2

Reserved (set to 0)

1:0

Programs length

00 = 2560 (48 kHz)

01 = 1280 (96 kHz digital IO only)

10 = 640 (192 kHz digital IO only)

11 = reserved

1 The polarity of this bit is inverted when read.

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