R1LV0416CBG-I Series

Rev.0.01, Jan.11.2005, page 7 of 14

Write Cycle

R1LV0416CBG-I

-5SI

-7LI

Parameter

Symbol

Min

Max

Min

Max

Unit

Notes

Write cycle time

55



70



ns

Address valid to end of write

50



60



ns

Chip selection to end of write

50



60



ns

5

Write pulse width

40



50



ns

4

LB#, UB# valid to end of write

50



55



ns

Address setup time

0



0



ns

6

Write recovery time

0



0



ns

7

Data to write time overlap

25



30



ns

Data hold from write time

0



0



ns

Output active from end of write

5



5



ns

2

Output disable to output in high-Z

0

20

0

25

ns

1, 2, 3

Write to output in high-Z

0

20

0

25

ns

1, 2

are not referred to output voltage levels.

2. This parameter is sampled and not 100% tested.

device to device.

4. A write occures during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A

write begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going

low or UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE#

write.