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AD7294 Datasheet(PDF) 6 Page - Analog Devices

Part No. AD7294
Description  12-Bit, Multichannel, DAC/ADC Temperature Sensor and Current Sense for Monitor and Control Applications
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7294 Datasheet(HTML) 6 Page - Analog Devices

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AD7294
Preliminary Technical Data
Rev. PrB | Page 6 of 45
TIMING CHARACTERISTICS1,2
I2C Serial Interface
DVDD = 4.5 V to 5.5 V, AGND = DGND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
FSCL
400
kHz max
SCL clock frequency
t1
2.5
µs min
SCL cycle time
t2
0.6
µs min
tHIGH, SCL high time
t3
1.3
µs min
tLOW, SCL low time
t4
0.6
µs min
tHD,STA, start/repeated start condition hold time
t5
100
ns min
tSU,DAT, data set-up time
t63
0.9
µs max
tHD,DAT, data hold time
0
µs min
tHD,DAT, data hold time
t7
0.6
µs min
tSU,STA, set-up time for repeated start
t8
0.6
µs min
tSU,STO, stop condition set-up time
t9
1.3
µs min
tBUF, bus free time between a stop and a start condition
t10
300
ns max
tR, rise time of SCL and SDA when receiving
0
ns min
tR, rise time of SCL and SDA when receiving (CMOS compatible)
t11
300
ns max
tF, fall time of SDA when transmitting
0
ns min
tF, fall time of SDA when receiving (CMOS compatible)
300
ns max
tF, fall time of SCL and SDA when receiving
20 + 0.1Cb4
ns min
tF, fall time of SCL and SDA when transmitting
Cb
400
pF max
Capacitive load for each bus line
1 Guaranteed by design and characterization; not subject to production test.
2 See Figure 2.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4 Cb is the total capacitance in pF of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t9
t3
t1
t11
t4
t10
t4
t5
t7
t6
t8
t2
SDA
SCL
Figure 2. I2C-Compatible Serial Interface Timing Diagram
CL
50pF
TO OUTPUT PIN
VOH (MIN) OR
VOL (MAX)
200
µA
200
µA
IOL
IOH
Figure 3. Load Circuit for Digital Output


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