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IDT74ALVCH16823 Datasheet(PDF) 2 Page - Integrated Device Technology

Part No. IDT74ALVCH16823
Description  3.3V CMOS 18-BIT BUS-INTERFACE FLIPFLOP WITH 3-STATE OUTPUTS AND BUS-HOLD
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT74ALVCH16823 Datasheet(HTML) 2 Page - Integrated Device Technology

   
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INDUSTRIALTEMPERATURERANGE
2
IDT74ALVCH16823
3.3VCMOS18-BITBUS-INTERFACEFLIP-FLOPWITH3-STATEOUTPUTS
TSSOP
TOP VIEW
PIN CONFIGURATION
NOTE:
1. As applicable to the device type.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
5
7
pF
COUT
Output Capacitance
VOUT = 0V
7
9
pF
COUT
I/O Port Capacitance
VIN = 0V
7
9
pF
CAPACITANCE (TA= +25°C, F = 1.0MHz)
Symbol
Description
Max
Unit
VTERM(2) Terminal Voltage with Respect to GND
–0.5 to +4.6
V
VTERM(3) Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
°C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
±50
mA
VI < 0 or VI > VCC
IOK
Continuous Clamp Current, VO < 0
–50
mA
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminals.
3. All terminals except VCC.
1
CLR
1
OE
1
Q1
GND
1
Q2
1
Q3
VCC
1
Q4
1
Q5
GND
1
Q6
1
Q7
1
Q8
1
Q9
2
Q2
2
Q3
GND
2
Q4
2
Q5
2
Q6
VCC
2
Q7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
1
CLK
1
CLKEN
1
D1
GND
1
D2
1
D3
VCC
1
D4
1
D5
1
D6
1
D7
1
D8
1
D9
GND
2
D2
2
D3
2
D4
2
D5
GND
2
D6
2
D7
2
D8
GND
2
Q9
2
OE
2
CLR
25
26
27
28
32
31
30
29
GND
2
D9
2
CLKEN
2
CLK
2
Q1
2
Q8
VCC
2
D1
FUNCTION TABLE (EACH 9-BITFLIP-FLOP)(1)
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
Inputs
Output
xOE
xCLR
xCLKEN
xCLK
xDx
xQx
L
L
XXX
L
LH
L
HH
LH
L
LL
LH
L
L
X
Q
0
(2)
LH
H
X
X
Q
0
(2)
H
X
XXX
Z
Pin Names
Description
xDx
Data Inputs(1)
xCLK
Clock Input
xCLKEN
Clock Enable Inputs
xQx
3-State Outputs
xOE
3-State Output Enable Inputs
xCLR
Clear Inputs
PIN DESCRIPTION
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.


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