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PI6C2952 Datasheet(PDF) 5 Page - Pericom Semiconductor Corporation

Part No. PI6C2952
Description  Low Voltage PLL Clock Driver
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Maker  PERICOM [Pericom Semiconductor Corporation]
Homepage  http://www.pericom.com

PI6C2952 Datasheet(HTML) 5 Page - Pericom Semiconductor Corporation

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Low Voltage PLL Clock Driver
In most high performance clock networks point–to–point distribu-
tion of signals is the method of choice. In a point–to–point scheme
either series terminated or parallel terminated transmission lines can
be used. The parallel technique terminates the signal at the end of
the line with a 50ohm resistance to VCC/2. This technique draws a
fairly high level of DC current and thus only a single terminated line
can be driven by each output of the PI6C2952 clock driver. For the
series terminated case however there is no DC current draw, thus the
outputs can drive multiple series terminated lines. Figure 3 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fanout of
the PI6C2952 clock driver is effectively doubled due to its capability
to drive multiple lines.
The waveform plots of Figure 4 show the simulation results of an
output driving a single line vs two lines. In both cases the drive
capability of the PI6C2952 output buffers is more than sufficient to
drive 50-ohm transmission lines on the incident edge. Note from the
delay measurements in the simulations a delta of only 43ps exists
between the two differently loaded outputs. This suggests that the
dual line driving need not be used exclusively to maintain the tight
output–to–output skew of the PI6C2952. The output waveform in
Figure 4 shows a step in the waveform, this step is caused by the
impedance mismatch seen looking into the driver. The parallel
combination of the 43ohm series resistor plus the output impedance
does not match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in this
case 4.0ns).
Figure 4. Single versus Dual Waveforms
Since this step is well above the threshold region it will not cause any
false clock triggering, however designers may be uncomfortable with
unwanted reflections on the line. To better match the impedances
when driving multiple lines the situation in Figure 5 should be used.
In this case the series terminating resistors are reduced such that
when the parallel combination is added to the output buffer imped-
ance the line impedance is perfectly matched.
RS = 36 ohms
RS = 36 ohms
ZO = 50 ohms
ZO = 50 ohms
7 ohms + 36 ohms
⏐ 36 ohms = 50 ohms ⏐ 50 ohms
25 ohms = 25 ohms
Figure 5. Optimized Dual Line Termination
SPICE level output buffer models are available for engineers who
want to simulate their specific interconnect schemes. In addition IV
characteristics are in the process of being generated to support the
other board level simulators in general use.
Power Supply Filtering
The PI6C2952 is a mixed analog/digital product and as such it exhibits
some sensitivities that would not necessarily be seen on a fully
digital product. Analog circuitry is naturally susceptible to random
noise, especially if this noise is seen on the power supply pins. The
PI6C2952 provides separate power supplies for the output buffers
(VCCO) and the internal PLL (VCCA) of the device. The purpose of this
design technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog phase–locked
loop. In a controlled environment such as an evaluation board this
level of isolation is sufficient. However, in a digital system environ-
ment where it is more difficult to minimize noise on the power supplies
a second level of isolation may be required. The simplest form of
isolation is a power supply filter on the VCCA pin for the PI6C2952.
TIME (ns)
tD = 3.8956
tD = 3.9386
trip delay (In this example: 4.0ns)
RS = 5-15 ohms
Figure 6. Power Supply Filter

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