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IDT72V36100L10BB Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT72V36100L10BB Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 48 page 11 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC IITM 36-BIT FIFO 65,536 x 36 and 131,072 x 36 APRIL 6, 2006 6117 drw04 330 Ω 30pF* 510 Ω 3.3V D.U.T. Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns(1) Input Timing Reference Levels 1.5V OutputReferenceLevels 1.5V Output Load for tCLK = 10ns, 15 ns See Figure 2a Output Load for tCLK = 6ns, 7.5ns See Figure 2b & 2c AC TEST CONDITIONS Figure 2b. AC Test Load Figure 2c. Lumped Capacitive Load, Typical Derating AC TEST LOADS - 6ns, 7.5ns Speed Grade Figure 2a. Output Load * Includes jig and scope capacitances. ACTESTLOADS-10ns,15nsSpeedGrades NOTE: 1. For 166MHz and 133MHz operation input rise/fall times are 1.5ns. 6117 drw04a 50 Ω 1.5V I/O Z0 = 50 Ω 6117 drw04b 6 5 4 3 2 1 20 30 50 80 100 200 Capacitance (pF) VIH OE VIL tOE & tOLZ VCC 2 VCC 2 100mV 100mV tOHZ 100mV 100mV Output Normally LOW Output Normally HIGH VOL VOH VCC 2 VCC 2 6117 drw04c Output Enable Output Disable OUTPUT ENABLE & DISABLE TIMING |
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