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TPS28225DRBT Datasheet(PDF) 4 Page - Texas Instruments |
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TPS28225DRBT Datasheet(HTML) 4 Page - Texas Instruments |
4 / 30 page www.ti.com 5 4 7 3 8 1 2 2 BOOT UGATE PHASE LGATE GND 1 8 5 4 6 VDD EN/PG 7 PWM 3 2 BOOT UGATE PHASE LGATE GND 1 8 5 4 6 VDD EN/PG 7 PWM 3 VIN PWM 4 GND VOUT PWM1 8 PWM3 Enable PWM2 ToDriver ToDriver GNDS ToController CSCN CS 4 ToController CS 1 VDD (4.5Vto8V) VIN (3Vto32V − VDD) TPS28225 TPS28225 VOUT TPS28225 SLUS710 – MAY 2006 TYPICAL APPLICATIONS (continued) Multi-Phase Synchronous Buck Converter ORDERING INFORMATION(1)(2)(3) TEMPERATURE RANGE, TA = TJ PACKAGE TAPE AND REEL QTY. PART NUMBER Plastic 8-pin SOIC (D) 250 TPS28225DT Plastic 8-pin SOIC (D) 2500 TPS28225DR -40°C to 125°C Plastic 8-pin DFN (DRB) 250 TPS28225DRBT Plastic 8-pin DFN (DRB) 3000 TPS28225DRBR (1) SOIC-8 (D) and DFN-8 (DRB) packages are available taped and reeled. Add T suffix to device type (e.g. TPS28225DT) to order taped devices and suffix R to device type to order reeled devices. (2) The SOIC-8 (D) and DFN-8 (DRB) package uses in Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations. (3) In the DFN package, the pad underneath the center of the device is a thermal substrate. The PCB “thermal land” design for this exposed die pad should include thermal vias that drop down and connect to one or more buried copper plane(s). This combination of vias for vertical heat escape and buried planes for heat spreading allows the DFN to achieve its full thermal potential. This pad should be either grounded for best noise immunity, and it should not be connected to other nodes. 4 Submit Documentation Feedback |
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