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ISPLSI1032-60 Datasheet(PDF) 5 Page - Lattice Semiconductor |
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ISPLSI1032-60 Datasheet(HTML) 5 Page - Lattice Semiconductor |
5 / 16 page Specifications ispLSI 1032 5 1. Unless noted otherwise, all parameters use a GRP load of 4 GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-Bit counter using GRP feedback. 4. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. 5. Reference Switching Test Conditions section. MIN. MAX. Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path Clock Frequency with Internal Feedback3 Clock Frequency with External Feedback Clock Frequency, Max Toggle4 GLB Reg. Setup Time before Clock, 4PT bypass GLB Reg. Clock to Output Delay, ORP bypass GLB Reg. Hold Time after Clock, 4 PT bypass GLB Reg. Setup Time before Clock GLB Reg. Clock to Output Delay GLB Reg. Hold Time after Clock Ext. Reset Pin to Output Delay Ext. Reset Pulse Duration Input to Output Enable Input to Output Disable Ext. Sync. Clock Pulse Duration, High Ext. Sync. Clock Pulse Duration, Low I/O Reg. Setup Time before Ext. Sync. Clock (Y2, Y3) I/O Reg. Hold Time after Ext. Sync. Clock (Y2, Y3) ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns tpd1 tpd2 fmax (Int.) fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 ten tdis twh twl tsu5 th5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 A A A – – – A – – – – A – B C – – – – DESCRIPTION1 PARAMETER # 2 UNITS TEST 5 COND. 1 tsu2 + tco1 ( ) MIN. MAX. – – 80 50 100 7 – 0 10 – 0 – 10 – – 5 5 2 6.5 15 20 – – – – 10 – – 12 – 17 – 18 18 – – – – – – 60 38 83 9 – 0 13 – 0 – 13 – – 6 6 2.5 8.5 20 25 – – – – 13 – – 16 – 22.5 – 24 24 – – – – -80 -60 MIN. MAX. – – 90.9 58.8 125 6 – 0 9 – 0 – 10 – – 4 4 2 6.5 12 17 – – – – 8 – – 10 – 15 – 15 15 – – – – -90 Table 2-0030-32/90,80,60C External Timing Parameters Over Recommended Operating Conditions |
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