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ISPLSI1032 Datasheet(PDF) 1 Page - Lattice Semiconductor

Part No. ISPLSI1032
Description  In-System Programmable High Density PLD
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Maker  LATTICE [Lattice Semiconductor]
Homepage  http://www.latticesemi.com
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ISPLSI1032 Datasheet(HTML) 1 Page - Lattice Semiconductor

 
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ispLSI® 1032
In-System Programmable High Density PLD
Features
• HIGH-DENSITY PROGRAMMABLE LOGIC
— High Speed Global Interconnect
— 6000 PLD Gates
— 64 I/O Pins, Eight Dedicated Inputs
— 192 Registers
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Fast Random Logic
— Security Cell Prevents Unauthorized Copying
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 90 MHz Maximum Operating Frequency
fmax = 60 MHz for Industrial and Military/883 Devices
tpd = 12 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile E2CMOS Technology
— 100% Tested
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable™ (ISP™) 5-Volt Only
— Increased Manufacturing Yields, Reduced Time-to-
Market, and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• COMBINES EASE OF USE AND THE FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEX-
IBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Four Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
1032_07
Functional Block Diagram
Output Routing Pool
Output Routing Pool
D7 D6 D5 D4 D3 D2 D1 D0
B0 B1 B2 B3 B4 B5 B6 B7
A0
A1
A2
A3
A4
A5
A6
A7
C7
C6
C5
C4
C3
C2
C1
C0
CLK
Global Routing Pool (GRP)
Logic
Array
DQ
DQ
DQ
DQ
GLB
Description
The ispLSI 1032 is a High-Density Programmable Logic
Device containing 192 Registers, 64 Universal I/O pins,
eight Dedicated Input pins, four Dedicated Clock Input
pins and a Global Routing Pool (GRP). The GRP pro-
vides complete interconnectivity between all of these
elements. The ispLSI 1032 features 5-Volt in-system
programming and in-system diagnostic capabilities. It is
the first device which offers non-volatile reprogrammability
of the logic, as well as the interconnect to provide truly
reconfigurable systems.
The basic unit of logic on the ispLSI 1032 device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see figure 1). There are a total of 32 GLBs in the
ispLSI 1032 device. Each GLB has 18 inputs, a program-
mable AND/OR/XOR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
other GLB on the device.
Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
March 1999
Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com


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