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PRELIMINARY
CY7C1513V18
CY7C1526V18
CY7C1511V18
CY7C1515V18
Document #: 38-05363 Rev. *A
Page 3 of 23
Logic Block Diagram (CY7C1513V18)
CLK
A(19:0)
Gen.
K
K
Control
Logic
Address
Register
D[17:0]
Read Data Reg.
RPS
WPS
Q[17:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
18
72
18
BWS[1:0]
VREF
Write
Reg
36
A(19:0)
20
C
C
Write
Reg
Write
Reg
Write
Reg
18
CQ
CQ
DOFF
Logic Block Diagram (CY7C1515V18)
CLK
A(18:0)
Gen.
K
K
Control
Logic
Address
Register
D[35:0]
Read Data Reg.
RPS
WPS
Q[35:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
72
19
36
144
36
BWS[3:0]
VREF
Write
Reg
72
A(18:0)
19
C
C
Write
Reg
Write
Reg
Write
Reg
36
CQ
CQ
DOFF
Selection Guide
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
250
200
167
MHz
Maximum Operating Current
TBD
TBD
TBD
mA
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