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PRELIMINARY
CY7C1513V18
CY7C1526V18
CY7C1511V18
CY7C1515V18
Document #: 38-05363 Rev. *A
Page 2 of 23
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Logic Block Diagram (CY7C1511V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[7:0]
Read Data Reg.
RPS
WPS
Q[7:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
16
21
8
32
8
NWS[1:0]
VREF
Write
Reg
16
A(20:0)
21
C
C
Write
Reg
Write
Reg
Write
Reg
8
CQ
CQ
DOFF
Logic Block Diagram (CY7C1526V18)
CLK
A(20:0)
Gen.
K
K
Control
Logic
Address
Register
D[8:0]
Read Data Reg.
RPS
WPS
Q[8:0]
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
9
36
9
BWS[0]
VREF
Write
Reg
18
A(20:0)
21
C
C
Write
Reg
Write
Reg
Write
Reg
9
CQ
CQ
DOFF