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CY7C1513V18 Datasheet(PDF) 9 Page - Cypress Semiconductor

Part # CY7C1513V18
Description  72-Mbit QDR??II SRAM 4-Word Burst Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1513V18 Datasheet(HTML) 9 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1513V18
CY7C1526V18
CY7C1511V18
CY7C1515V18
Document #: 38-05363 Rev. *A
Page 9 of 23
Application Example[1]
Truth Table[ 2, 3, 4, 5, 6, 7]
Operation
K
RPS
WPS
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising
edge of K; input write data on
two consecutive K and K
rising edges.
L-H
H[8]
L[9]
D(A) at
K(t+1)
D(A + 1) at
K(t+1)
D(A + 2) at K(t
+ 2)
D(A + 3) at
K(t +2)
Read Cycle:
Load address on the rising
edge of K; wait one and a
half cycle; read data on two
consecutive C and C rising
edges.
L-H
L[9]
X
Q(A) at
C(t +1)
Q(A + 1) at
C(t + 2)
Q(A + 2) at C(t
+ 2)
Q(A + 3) at C(t
+ 3)
NOP: No Operation
L-H
H
H
D=X
Q=High-Z
D=X
Q=High-Z
D=X
Q=High-Z
D=X
Q=High-Z
Standby: Clock Stopped
Stopped
X
X
Previous State Previous State Previous
State
Previous State
Write Cycle Descriptions CY7C1511V18 and CY7C1526V18) [2, 10]
BWS0/NWS0 BWS1/NWS1
KK
Comments
L
L
L–H
– During the Data portion of a Write sequence
:
CY7C1511V18
− both nibbles (D[7:0]) are written into the device,
CY7C1513V18
− both bytes (D[17:0]) are written into the device.
L
L
L-H During the Data portion of a Write sequence
:
CY7C1511V18
− both nibbles (D[7:0]) are written into the device,
CY7C1513V18
− both bytes (D[17:0]) are written into the device.
Notes:
1. The above application shows four QDRII being used.
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device will power-up deselected and the outputs in a tri-state condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the
“t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line
charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will
ignore the second Read or Write request.
10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table.NWS0, NWS1,BWS0, BWS1 ,BWS2 and BWS3 can be altered on different
portions of a write cycle, as long as the set-up and hold requirements are achieved.
Vt = Vddq/2
CC#
D
A
K
CC#
D
A
K
BUS
MASTER
(CPU
or
ASIC)
SRAM #1
SRAM #4
DATA IN
DATA OUT
Address
RPS#
WPS#
BWS#
Source K
Source K#
Delayed K
Delayed K#
R = 50
ohms
R = 250
ohms
R = 250
ohms
R
P
S
#
W
P
S
#
B
W
S
#
R
P
S
#
W
P
S
#
B
W
S
#
Vt
Vt
Vt
R
R
R
ZQ
CQ/CQ#
Q
K#
ZQ
CQ/CQ#
Q
K#
CLKIN/CLKIN#


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