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87C58X2 Datasheet(PDF) 38 Page - NXP Semiconductors |
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87C58X2 Datasheet(HTML) 38 Page - NXP Semiconductors |
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38 / 62 page  Philips Semiconductors Product data P80C3xX2; P80C5xX2; P87C5xX2 80C51 8-bit microcontroller family 4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V), low power, high speed (30/33 MHz) 2003 Jan 24 38 DC ELECTRICAL CHARACTERISTICS Tamb = 0 °C to +70 °C or –40 °C to +85 °C; VCC = 2.7 V to 5.5 V; VSS = 0 V (16 MHz max. CPU clock) SYMBOL PARAMETER TEST CONDITIONS LIMITS UNIT MIN TYP1 MAX VIL Input low voltage11 4.0 V < VCC < 5.5 V –0.5 0.2 VCC–0.1 V 2.7 V < VCC < 4.0 V –0.5 0.7 VCC V VIH Input high voltage (ports 0, 1, 2, 3, EA) – 0.2 VCC+0.9 VCC+0.5 V VIH1 Input high voltage, XTAL1, RST11 – 0.7 VCC VCC+0.5 V VOL Output low voltage, ports 1, 2, 8 VCC = 2.7 V; IOL = 1.6 mA2 – 0.4 V VOL1 Output low voltage, port 0, ALE, PSEN8, 7 VCC = 2.7 V; IOL = 3.2 mA2 – 0.4 V VOH Output high voltage, ports 1, 2, 3 3 VCC = 2.7 V; IOH = –20 mA VCC – 0.7 – V VCC = 4.5 V; IOH = –30 mA VCC – 0.7 – V VOH1 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 VCC = 2.7 V; IOH = –3.2 mA VCC – 0.7 – V IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 mA ITL Logical 1-to-0 transition current, ports 1, 2, 36 VIN = 2.0 V; See note 4 – –650 mA ILI Input leakage current, port 0 0.45 < VIN < VCC – 0.3 – ±10 mA ICC Power supply current (see Figure 34 and Source Code): Active mode @ 16 MHz mA Idle mode @ 16 MHz mA Power-down mode or clock stopped (see Figure 30 for conditions) 12 Tamb = 0 °C to 70 °C 2 30 mA Tamb = –40 °C to +85 °C 3 50 mA VRAM RAM keep-alive voltage – 1.2 V RRST Internal reset pull-down resistor – 40 225 k Ω CIO Pin capacitance10 (except EA) – – 15 pF NOTES: 1. Typical ratings are not guaranteed. Values listed are based on tests conducted on limited number of samples at room temperature. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100 pF), the noise pulse on the ALE pin may exceed 0.8 V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5 mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2 V. 5. See Figures 36 through 39 for ICC test conditions and Figure 34 for ICC vs. Frequency 12-clock mode characteristics: Active mode (operating): ICC = 1.0 mA + 0.9 mA × FREQ.[MHz] Active mode (reset): ICC = 7.0 mA + 0.5 mA x FREQ.[MHz] Idle mode: ICC = 1.0 mA + 0.18 mA x FREQ.[MHz] 6. This value applies to Tamb = 0 °C to +70 °C. For Tamb = –40 °C to +85 °C, ITL = –750 mA. 7. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 15 mA (*NOTE: This is 85 °C specification.) Maximum IOL per 8-bit port: 26 mA Maximum total IOL for all outputs: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF (except EA is 25 pF). 11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection circuitry has been added to the INT0 and INT1 pins. Previous devices provided only an inherent 5 ns of glitch rejection. 12. Power down mode for 3 V range: Commercial Temperature Range – typ: 0.5 mA, max. 20 mA; Industrial Temperature Range – typ. 1.0 mA, max. 30 mA; |
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