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89C51 Datasheet(PDF) 22 Page - NXP Semiconductors |
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89C51 Datasheet(HTML) 22 Page - NXP Semiconductors |
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22 / 32 page  Philips Semiconductors Product specification 89C51/89C52/89C54/89C58 80C51 8-bit microcontroller family 4K/8K/16K/32K Flash 1999 Oct 27 22 AC ELECTRICAL CHARACTERISTICS Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5 V ±10%, VSS = 0V1, 2, 3 VARIABLE CLOCK4 33MHz CLOCK SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT 1/tCLCL 14 Oscillator frequency Speed versions: I;J;U (33 MHz) 3.5 33 3.5 33 MHz tLHLL 14 ALE pulse width 2tCLCL–40 21 ns tAVLL 14 Address valid to ALE low tCLCL–25 5 ns tLLAX 14 Address hold after ALE low tCLCL–25 5 ns tLLIV 14 ALE low to valid instruction in 4tCLCL–65 55 ns tLLPL 14 ALE low to PSEN low tCLCL–25 5 ns tPLPH 14 PSEN pulse width 3tCLCL–45 45 ns tPLIV 14 PSEN low to valid instruction in 3tCLCL–60 30 ns tPXIX 14 Input instruction hold after PSEN 0 0 ns tPXIZ 14 Input instruction float after PSEN tCLCL–25 5 ns tAVIV 14 Address to valid instruction in 5tCLCL–80 70 ns tPLAZ 14 PSEN low to address float 10 10 ns Data Memory tRLRH 15, 16 RD pulse width 6tCLCL–100 82 ns tWLWH 15, 16 WR pulse width 6tCLCL–100 82 ns tRLDV 15, 16 RD low to valid data in 5tCLCL–90 60 ns tRHDX 15, 16 Data hold after RD 0 0 ns tRHDZ 15, 16 Data float after RD 2tCLCL–28 32 ns tLLDV 15, 16 ALE low to valid data in 8tCLCL–150 90 ns tAVDV 15, 16 Address to valid data in 9tCLCL–165 105 ns tLLWL 15, 16 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns tAVWL 15, 16 Address valid to WR low or RD low 4tCLCL–75 45 ns tQVWX 15, 16 Data valid to WR transition tCLCL–30 0 ns tWHQX 15, 16 Data hold after WR tCLCL–25 5 ns tQVWH 16 Data valid to WR high 7tCLCL–130 80 ns tRLAZ 15, 16 RD low to address float 0 0 ns tWHLH 15, 16 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns External Clock tCHCX 18 High time 17 tCLCL–tCLCX ns tCLCX 18 Low time 17 tCLCL–tCHCX ns tCLCH 18 Rise time 5 ns tCHCL 18 Fall time 5 ns Shift Register tXLXL 17 Serial port clock cycle time 12tCLCL 360 ns tQVXH 17 Output data setup to clock rising edge 10tCLCL–133 167 ns tXHQX 17 Output data hold after clock rising edge 2tCLCL–80 50 ns tXHDX 17 Input data hold after clock rising edge 0 0 ns tXHDV 17 Clock rising edge to input data valid 10tCLCL–133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF. 3. Interfacing the microcontroller to devices with float times up to 45 ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Parts are guaranteed to operate down to 0 Hz. |
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