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87LPC768 Datasheet(PDF) 9 Page - NXP Semiconductors |
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87LPC768 Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 64 page Philips Semiconductors Preliminary data 87LPC768 Low power, low price, low pin count (20 pin) microcontroller with 4 kB OTP 8-bit A/D, Pulse Width Modulator 2001 Aug 06 7 Table 1. Special Function Registers Name Description SFR Address Bit Functions and Addresses MSB LSB Reset Value E7 E6 E5 E4 E3 E2 E1 E0 ACC* Accumulator E0h 00h C7 C6 C5 C4 C3 C2 C1 C0 ADCON#* A/D Control C0h ENADC – – ADCI ADCS RCCLK AADR1 AADR0 00h AUXR1# Auxiliary Function Register A2h KBF BOD BOI LPEP SRST 0 – DPS 02h1 F7 F6 F5 F4 F3 F2 F1 F0 B* B register F0h 00h CMP1# Comparator 1 control register ACh – – CE1 CP1 CN1 OE1 CO1 CMF1 00h1 CMP2# Comparator 2 control register ADh – – CE2 CP2 CN2 OE2 CO2 CMF2 00h1 CNSW0 PWM Counter Shadow Register 0 D1h CNSW7 CNSW6 CNSW5 CNSW4 CNSW3 CNSW2 CNSW1 CNSW0 FFh CNSW1 PWM Counter Shadow Register 1 D2h – – – – – – CNSW9 CNSW8 FFh CPSW0 PWM Compare Shadow Register 0 D3h CPSW07 CPSW06 CPSW05 CPSW04 CPSW03 CPSW02 CPSW01 CPSW00 00h CPSW1 PWM Compare Shadow Register 1 D4h CPSW17 CPSW16 CPSW15 CPSW14 CPSW13 CPSW12 CPSW11 CPSW10 00h CPSW2 PWM Compare Shadow Register 2 D5h CPSW27 CPSW26 CPSW25 CPSW24 CPSW23 CPSW22 CPSW21 CPSW20 00h CPSW3 PWM Compare Shadow Register 3 D6h CPSW37 CPSW36 CPSW35 CPSW34 CPSW33 CPSW32 CPSW31 CPSW30 00h CPSW4 PWM Compare Shadow Register 4 D7h CPSW39 CPSW38 CPSW29 CPSW28 CPSW19 CPSW18 CPSW09 CPSW08 00h DAC0# A/D Result C5h 00h DIVM# CPU clock divide-by-M control 95h 00h DPTR: Data pointer (2 bytes) DPH Data pointer high byte 83h 00h DPL Data pointer low byte 82h 00h CF CE CD CC CB CA C9 C8 I2CFG#* I2C configuration register C8h/RD SLAVEN MASTRQ 0 TIRUN – – CT1 CT0 00h1 C8h/WR SLAVEN MASTRQ CLRTI TIRUN – – CT1 CT0 DF DE DD DC DB DA D9 D8 I2CON#* I2C control register D8h/RD RDAT ATN DRDY ARL STR STP MASTER – 80h1 D8h/WR CXA IDLE CDR CARL CSTR CSTP XSTR XSTP I2DAT# I2C data register D9h/RD RDAT 0 0 0 0 0 0 0 80h D9h/WR XDAT x x x x x x x AF AE AD AC AB AA A9 A8 IEN0* Interrupt enable 0 A8h EA EWD EBO ES ET1 EX1 ET0 EX0 00h EF EE ED EC EB EA E9 E8 IEN1#* Interrupt enable 1 E8h ETI – EC1 EAD – EC2 EKB EI2 00h1 BF BE BD BC BB BA B9 B8 IP0* Interrupt priority 0 B8h – PWD PBO PS PT1 PX1 PT0 PX0 00h1 IP0H# Interrupt priority 0 high byte B7h – PWDH PBOH PSH PT1H PX1H PT0H PX0H 00h1 FF FE FD FC FB FA F9 F8 IP1* Interrupt priority 1 F8h PTI – PC1 PAD – PC2 PKB PI2 00h1 IP1H# Interrupt priority 1 high byte F7h PTIH – PC1H PADH – PC2H PKBH PI2H 00h1 |
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