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LVX157 Datasheet(PDF) 4 Page - ON Semiconductor |
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LVX157 Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 6 page MC74LVX157 http://onsemi.com 4 AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns) TA = 25°C TA = − 40 to 85°C Symbol Parameter Test Conditions Min Typ Max Min Max Unit tPLH, tPHL Propagation Delay, Input to Output VCC = 2.7V CL = 15pF CL = 50pF − − 6.6 9.1 12.5 16.0 1.0 1.0 15.5 19.0 ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF − − 5.1 7.6 7.9 11.4 1.0 1.0 9.5 13.0 tPLH, tPHL Propagation Delay, S to Zn VCC = 2.7V CL = 15pF CL = 50pF − − 8.9 11.4 16.9 20.4 1.0 1.0 20.5 24.0 ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF − − 7.0 9.5 11.0 14.5 1.0 1.0 13.0 16.5 tPLH, tPHL Propagation Delay, E to Zn VCC = 2.7V CL = 15pF CL = 50pF − − 9.1 11.6 17.6 21.1 1.0 1.0 20.5 24.0 ns VCC = 3.3 ± 0.3V CL = 15pF CL = 50pF − − 7.2 9.7 11.5 15.0 1.0 1.0 13.5 17.0 tOSHL tOSLH Output−to−Output Skew (Note 1) VCC = 2.7V CL = 50pF VCC = 3.3 ±0.3V CL = 50pF − − − − 1.5 1.5 − − 1.5 1.5 ns 1. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. CAPACITIVE CHARACTERISTICS TA = 25°C TA = − 40 to 85°C Symbol Parameter Min Typ Max Min Max Unit Cin Input Capacitance − 4 10 − 10 pF CPD Power Dissipation Capacitance (Note 2) − 20 − − − pF 2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 4 (per bit). CPD is used to determine the no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 3.3V, Measured in SOIC Package) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.3 0.5 V VOLV Quiet Output Minimum Dynamic VOL −0.3 −0.5 V VIHD Minimum High Level Dynamic Input Voltage − 2.0 V VILD Maximum Low Level Dynamic Input Voltage − 0.8 V In or S E tPLH tPHL VCC GND 50% 50% VCC Zn VCC GND Zn tPHL tPLH 50% 50% VCC *Includes all probe and jig capacitance CL* TEST POINT DEVICE UNDER TEST OUTPUT Figure 3. Figure 4. Figure 5. Propagation Delay Test Circuit |
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