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83C752 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. 83C752
Description  80C51 8-bit microcontroller family 2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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83C752 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
83C752/87C752
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I2C, PWM, low pin count
1998 May 01
5
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
VSS
12
I
Circuit Ground Potential.
VCC
28
I
Supply voltage during normal, idle, and power-down operation.
P0.0–P0.4
8–6
23, 24
I/O
Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0–P0.2 are open drain. Port 0.0–P0.2 pins that have
1s written to them float, and in that state can be used as high-impedance inputs. P0.3–P0.4 are
bidirectional I/O port pins with internal pull-ups. Port 0 also serves as the serial I2C interface. When this
feature is activated by software, SCL and SDA are driven low in accordance with the I2C protocol.
These pins are driven low if the port register bit is written with a 0 or if the I2C subsystem presents a 0.
The state of the pin can always be read from the port register by the program. Port 0.3 and 0.4 have
internal pull-ups that function identically to port 3. Pins that have 1s written to them are pulled high by
the internal pull-ups and can be used as inputs.
To comply with the I2C specification, P0.0 and P0.1 are open drain bidirectional I/O pins with the
electrical characteristics listed in the tables that follow. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O in non-I2C
applications.
6
I
VPP (P0.2) – Programming voltage input. (See Note 2.)
7
I
OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8
I
ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0–P1.7
13–17,
20–22
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. P0.3–P0.4 pins are
bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will
source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also
serves the special function features of the SC80C51 family as listed below:
20
I
INT0 (P1.5): External interrupt.
21
I
INT1 (P1.6): External interrupt.
22
I
T0 (P1.7): Timer 0 external input.
13–17
I
ADC0 (P1.0)–ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D
converter. These pins can be used as outputs only if the A/D function has been disabled. These pins
can be used as inputs while the A/D converter is enabled.
Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the
value to program into the selected address during the program mode.
P3.0–P3.7
5–1,
27–25
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to
them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are
externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
9
I
Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An
internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC.
After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device
in the programming state allowing programming address, data and VPP to be applied for programming
or verification purposes. The RESET serial sequence must be synchronized with the X1 input.
X1
11
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1
also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2
10
O
Crystal 2: Output from the inverting oscillator amplifier.
AVCC 1
19
I
Analog supply voltage and reference input.
AVSS 1
18
I
Analog supply and reference ground.
NOTE:
1. AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be
in the range 4.5V to 5.5V.
2. When P0.2 is at or close to 0V, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pull-up
(e.g., 2k
Ω).


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