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83C652 Datasheet(PDF) 13 Page - NXP Semiconductors

Part No. 83C652
Description  CMOS single-chip 8-bit microcontrollers
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

83C652 Datasheet(HTML) 13 Page - NXP Semiconductors

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Phlips Semiconductors
Product specification
80C652/83C652
CMOS single-chip 8-bit microcontrollers
1997 Dec 05
13
AC ELECTRICAL CHARACTERISTICS1, 2 (24 MHz type)
24MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
2
Oscillator frequency
3.5
24
MHz
tLHLL
2
ALE pulse width
43
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
17
tCLCL–25
ns
tLLAX
2
Address hold after ALE low
17
tCLCL–25
ns
tLLIV
2
ALE low to valid instruction in
102
4tCLCL–65
ns
tLLPL
2
ALE low to PSEN low
17
tCLCL–25
ns
tPLPH
2
PSEN pulse width
80
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
65
3tCLCL–60
ns
tPXIX
2
Input instruction hold after PSEN
0
0
ns
tPXIZ
2
Input instruction float after PSEN
17
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
128
5tCLCL–80
ns
tPLAZ
2
PSEN low to address float
10
10
ns
Data Memory
tRLRH
3, 4
RD pulse width
150
6tCLCL–100
ns
tWLWH
3, 4
WR pulse width
150
6tCLCL–100
ns
tRLDV
3, 4
RD low to valid data in
118
5tCLCL–90
ns
tRHDX
3, 4
Data hold after RD
0
0
ns
tRHDZ
3, 4
Data float after RD
55
2tCLCL–28
ns
tLLDV
3, 4
ALE low to valid data in
180
8tCLCL–150
ns
tAVDV
3, 4
Address to valid data in
210
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
75
175
3tCLCL–50
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
92
4tCLCL–75
ns
tQVWX
3, 4
Data valid to WR transition
12
tCLCL–30
ns
tDW
3, 4
Data setup time before WR
162
7tCLCL–130
ns
tWHQX
3, 4
Data hold after WR
17
tCLCL–25
ns
tRLAZ
3, 4
RD low to address float
0
0
ns
tWHLH
3, 4
RD or WR high to ALE high
17
67
tCLCL–25
tCLCL+25
ns
Shift Register
tXLXL
5
Serial port clock cycle time3
0.5
12tCLCL
µs
tQVXH
5
Output data setup to clock rising edge3
283
10tCLCL–133
ns
tXHQX
5
Output data hold after clock rising edge3
23
2tCLCL–60
ns
tXHDX
5
Input data hold after clock rising edge3
0
0
ns
tXHDV
5
Clock rising edge to input data valid3
283
10tCLCL–133
ns
External Clock
tCHCX
6
High time3
17
17
tCLCL – tCLCX
ns
tCLCX
6
Low time3
17
17
tCLCL – tCHCX
ns
tCLCH
6
Rise time3
5
5
ns
tCHCL
6
Fall time3
5
5
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. These values are characterized but not 100% production tested.


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