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CY7C1355C-100BZC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1355C-100BZC
Description  9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL Architecture
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1355C-100BZC Datasheet(HTML) 8 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1355C
CY7C1357C
Document #: 38-05539 Rev. **
Page 8 of 33
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If
the JTAG feature is not being utilized, this pin should be left unconnected. This pin
is not available on TQFP packages.
TDI
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be left floating or connected to VDD through
a pull up resistor. This pin is not available on TQFP packages.
TMS
JTAG serial
input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
feature is not being utilized, this pin can be disconnected or connected to VDD. This
pin is not available on TQFP packages.
TCK
JTAG-Clock
Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin
must be connected to VSS. This pin is not available on TQFP packages.
NC
-
No Connects. Not internally connected to the die.
18M,36M, 72M, 144M and 288M are address expansion pins and are not internally
connected to the die.
VSS/DNU
Ground/DNU
This pin can be connected to Ground or should be left floating.
Pin Definitions (continued)
Name
I/O
Description


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