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CD40105BMS Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # CD40105BMS
Description  CMOS FIFO Register
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

CD40105BMS Datasheet(HTML) 9 Page - Renesas Technology Corp

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CD40105BMS
FN3353 Rev 0.00
Page 9 of 10
December 1992
FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM
FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG
FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS
CONTROL LOGIC
4 x 16
DATA
REGISTER
13
12
11
10
1
14
15
9
4
5
6
7
2
3
INPUT
BUFFERS
OUTPUT
BUFFERS
Q0
Q1
Q2
Q3
3-STATE
CONTROL
D0
D1
D2
D3
DATA-IN
READY (DIR)
SHIFT IN (SI)
MASTER
RESET (MR)
DATA-OUT
READY (DOR)
SHIFT OUT (SO)
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI
DOR
DIR MR SO
D0
D1
D2
D3
Q0
Q1
Q2
Q3
SI
DOR
DIR MR SO
10
1 1
1
1 1
1
1
1
00
0
0
0
0
MASTER
RESET
SHIFT IN
(DATA VALID)
SHIFT OUT
INPUT READY
(CLEAR OUT)
OUTPUT READY
(CLEAR OUT)
DATA IN (Dn)
3-STATE
(OUTPUT
ENABLE)
DATA OUT
***
(UNKNOWN)
SHIFT-OUT PULSES
HAVE NO EFFECT
 2s
*
SHIFT-IN PULSES
HAVE NO EFFECT
 2s
**
HIGH
Z
INVALID
1
0
1
1
1
0
*AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16
**AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1
***DATA VALID goes to high level in advance of the DATA OUT
and 20ns at VDD = 15V for CL = 50pF and TA = 25oC
by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V,
INPUTS
OUTPUTS
INPUTS


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