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80C552 Datasheet(PDF) 13 Page - NXP Semiconductors

Part # 80C552
Description  Single-chip 8-bit microcontroller
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

80C552 Datasheet(HTML) 13 Page - NXP Semiconductors

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Philips Semiconductors
Product data
80C552/83C552
Single-chip 8-bit microcontroller with 10-bit A/D,
capture/compare timer, high-speed outputs, PWM
2002 Sep 03
13
AC ELECTRICAL CHARACTERISTICS1, 2
16 MHz version
16 MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
2
Oscillator frequency
3.5
16
MHz
tLHLL
2
ALE pulse width
85
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
8
tCLCL–55
ns
tLLAX
2
Address hold after ALE low
28
tCLCL–35
ns
tLLIV
2
ALE low to valid instruction in
150
4tCLCL–100
ns
tLLPL
2
ALE low to PSEN low
23
tCLCL–40
ns
tPLPH
2
PSEN pulse width
143
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
83
3tCLCL–105
ns
tPXIX
2
Input instruction hold after PSEN
0
0
ns
tPXIZ
2
Input instruction float after PSEN
38
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
208
5tCLCL–105
ns
tPLAZ
2
PSEN low to address float
10
10
ns
Data Memory
tRLRH
3
RD pulse width
275
6tCLCL–100
ns
tWLWH
4
WR pulse width
275
6tCLCL–100
ns
tRLDV
3
RD low to valid data in
148
5tCLCL–165
ns
tRHDX
3
Data hold after RD
0
0
ns
tRHDZ
3
Data float after RD
55
2tCLCL–70
ns
tLLDV
3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
3
Address to valid data in
398
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
138
238
3tCLCL–50
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
120
4tCLCL–130
ns
tQVWX
4
Data valid to WR transition
3
tCLCL–60
ns
tDW
4
Data before WR
288
7tCLCL–150
ns
tWHQX
4
Data hold after WR
13
tCLCL–50
ns
tRLAZ
3
RD low to address float
0
0
ns
tWHLH
3, 4
RD or WR high to ALE high
23
103
tCLCL–40
tCLCL+40
ns
External Clock
tCHCX
5
High time4
20
20
ns
tCLCX
5
Low time4
20
20
ns
tCLCH
5
Rise time4
20
20
ns
tCHCL
5
Fall time4
20
20
ns
Serial Timing – Shift Register Mode4 (Test Conditions: Tamb = 0 °C to +70 °C; VSS = 0 V; Load Capacitance = 80 pF)
tXLXL
6
Serial port clock cycle time
0.75
12tCLCL
µs
tQVXH
6
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
6
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
6
Input data hold after clock rising edge
0
0
ns
tXHDV
6
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100 pF, load capacitance for all other outputs = 80 pF.
3. tCLCL = 1/fOSC = one oscillator clock period.
tCLCL = 83.3ns at fOSC = 12 MHz.
tCLCL = 62.5ns at fOSC = 16 MHz.
4. These values are characterized but not 100% production tested.


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