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80C550 Datasheet(PDF) 17 Page - NXP Semiconductors

Part No. 80C550
Description  80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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80C550 Datasheet(HTML) 17 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
80C550/83C550/87C550
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
1998 May 01
17
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10% (87C550), VCC = 5V ±20% (80/83C550), VSS = 0V1, 2
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
5
Oscillator frequency: Speed Versions
S8XC550 Exx
3.5
16
MHz
tLHLL
5
ALE pulse width
85
2tCLCL–40
ns
tAVLL
5
Address valid to ALE low
7
tCLCL–55
ns
tLLAX
5
Address hold after ALE low
27
tCLCL–35
ns
tLLIV
5
ALE low to valid instruction in
150
4tCLCL–100
ns
tLLPL
5
ALE low to PSEN low
22
tCLCL–40
ns
tPLPH
5
PSEN pulse width
142
3tCLCL–45
ns
tPLIV
5
PSEN low to valid instruction in
82
3tCLCL–105
ns
tPXIX
5
Input instruction hold after PSEN
0
0
ns
tPXIZ
5
Input instruction float after PSEN
37
tCLCL–25
ns
tAVIV
5
Address to valid instruction in
207
5tCLCL–105
ns
tPLAZ
5
PSEN low to address float
10
10
ns
Data Memory
tRLRH
6, 7
RD pulse width
275
6tCLCL–100
ns
tWLWH
6, 7
WR pulse width
275
6tCLCL–100
ns
tRLDV
6, 7
RD low to valid data in
212
5tCLCL–165
ns
tRHDX
6, 7
Data hold after RD
0
0
ns
tRHDZ
6, 7
Data float after RD
55
2tCLCL–70
ns
tLLDV
6, 7
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
6, 7
Address to valid data in
397
9tCLCL–165
ns
tLLWL
6, 7
ALE low to RD or WR low
137
247
3tCLCL–50
3tCLCL+50
ns
tAVWL
6, 7
Address valid to WR low or RD low
120
4tCLCL–130
ns
tQVWX
6, 7
Data valid to WR transition
12
tCLCL–50
ns
tWHQX
6, 7
Data hold after WR
12
tCLCL–50
ns
tRLAZ
6, 7
RD low to address float
0
0
ns
tWHLH
6, 7
RD or WR high to ALE high
22
102
tCLCL–40
tCLCL+40
ns
External Clock
tCHCX
9
High time
20
20
ns
tCLCX
9
Low time
20
20
ns
tCLCH
9
Rise time
20
20
ns
tCHCL
9
Fall time
20
20
ns
Shift Register
tXLXL
8
Serial port clock cycle time
750
12tCLCL
ns
tQVXH
8
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
8
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
8
Input data hold after clock rising edge
0
0
ns
tXHDV
8
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.


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