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MC74F195 Datasheet(PDF) 1 Page - Motorola, Inc

Part No. MC74F195
Description  4-BIT PARALLEL ACCESS SHIFT REGISTER
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Maker  MOTOROLA [Motorola, Inc]
Homepage  http://www.freescale.com
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MC74F195 Datasheet(HTML) 1 Page - Motorola, Inc

   
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4-104
FAST AND LS TTL DATA
4-BIT PARALLEL
ACCESS SHIFT REGISTER
The functional characteristics of the MC74F195 4-Bit Parallel Access Shift
Register are indicated in the Logic Diagram and Function Table. The device
is useful in a wide variety of shifting, counting, and storage applications. It per-
forms serial, parallel, serial-to-parallel, or parallel-to-serial data transfers at
very high speeds.
The MC74F195 operates in two primary modes, shift right (Q0-Q1) and par-
allel load, which are controlled by the state of the Parallel Enable (PE) input.
Serial data enters the first flip-flop (Q0) via the J and K inputs when the PE
input is HIGH, and is shifted 1 bit in the direction Q0-Q1-Q2-Q3 following each
LOW-to-HIGH clock transition. The J and K inputs provide the flexibility of the
JK type input is made for special applications, and by tying the two pins togeth-
er the simple D-type input is made for general applications. The device ap-
pears as four common clocked D flip-flops when the PE input is LOW. After
the LOW-to-HIGH clock transition, data on the parallel inputs (D0-D3) is trans-
ferred to the respective Q0-Q3 outputs. Shift left operation (Q3-Q2) can be
achieved by tying the Qn outputs to the Dn-1 inputs and holding the PE input
LOW.
All parallel and serial data transfers are synchronous, occurring after each
LOW-to-HIGH clock transition.
The MC74F195 utilizes edge-triggering;
therefore, there is no restriction on the activity of the J, K, Dn, and PE inputs
for logic operation, other than the setup and hold time requirements.
A LOW on the asynchronous Master Reset (MR) input sets all Q outputs
LOW, independent of any other input condition.
Shift Right and Parallel Load Capability
J-K (D-Type) Inputs to First Stage
Complement Output from Last Stage
Asynchronous Master Reset
CONNECTION DIAGRAM DIP
15
16
14
13
12
11
10
2
1
3
4
5
6
7
VCC
9
8
Q0
Q1
Q2
Q3
Q3
CP
PE
MR
J
K
D0
D1
D2
D3
GND
MC74F195
4-BIT PARALLEL
ACCESS SHIFT REGISTER
FAST
™ SCHOTTKY TTL
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
16
1
16
1
ORDERING INFORMATION
MC74FXXXJ
Ceramic
MC74FXXXN
Plastic
MC74FXXXD
SOIC
16
1
D SUFFIX
SOIC
CASE 751B-03
LOGIC SYMBOL
PE D0 D1 D2 D3
J
K
CP
MR Q0 Q1 Q2 Q3
Q3
VCC = PIN 16
GND = PIN 8
9
5
6
7
2
3
10
11
1 15 14 13 12
4


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