128K x 8 Static RAM
CY7C1009V33
CY7C109V33
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
September 3, 1999
Features
• High speed
—tAA = 15, 20, 25ns
•VCC = 3.3V ± 10%
• Low active power
— 432 mW (max.)
— 288 mW (L version)
• Low CMOS standby power
— 18 mW (max.)
— 7.2 mW (L version)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE1, CE2, and OE options
Functional Description
The CY7C109V33/CY7C1009V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE1), an active HIGH Chip Enable (CE2), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable one (CE1) and Write
Enable (WE) inputs LOW and Chip Enable two (CE2) input
HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then
written into the location specified on the address pins (A0
through A16).
Reading from the device is accomplished by taking Chip En-
able one (CE1) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE2) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE1
HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE1 LOW, CE2 HIGH, and WE LOW).
The
CY7C109V33
is
available
in
standard
32-pin,
400-mil-wide SOJ package. The CY7C1009V33 is available in
a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and
CY7C109V33 are functionally equivalent in all other respects.
Shaded areas contain preliminary information.
Selection Guide
7C109V33-12
7C1009V33-12
7C109V33-15
7C1009V33-15
7C109V33-20
7C1009V33-20
7C109V33-25
7C1009V33-25
Maximum Access Time (ns)
12
15
20
20
Maximum Operating Current (mA)
130
120
110
110
Maximum Operating Current (mA) Low Power Version
90
80
70
70
Maximum CMOS Standby Current (mA) Standard
5
555
Maximum CMOS Standby Current (mA) Low Power Version
2
222
Logic Block Diagram
Pin Configurations
A1
A2
A3
A4
A5
A6
A7
A8
COLUMN
DECODER
INPUT BUFFER
POWER
DOWN
WE
OE
I/O0
CE2
I/O1
I/O2
I/O3
512 x 256 x 8
ARRAY
I/O7
I/O6
I/O5
I/O4
A0
CE1
1
2
3
4
5
6
7
8
9
10
11
14
19
20
24
23
22
21
25
28
27
26
Top View
SOJ
12
13
29
32
31
30
16
15
17
18
GND
A16
A14
A12
A7
A6
A5
A4
A3
WE
VCC
A15
A13
A8
A9
I/O7
I/O6
I/O5
I/O4
109V33–1
A2
NC
I/O0
I/O1
I/O2
CE1
OE
A10
I/O3
A1
A0
A11
CE2
109V33–2
A6
A7
A16
A14
A12
WE
VCC
A4
A13
A8
A9
OE
TSOP I
Top View
(not to scale)
1
6
2
3
4
5
7
32
27
31
30
29
28
26
21
25
24
23
22
19
20
I/O2
I/O1
GND
I/O7
I/O4
I/O5
I/O6
I/O0
CE
A11
A5
17
18
8
9
10
11
12
13
14
15
16
CE2
A15
NC
A10
I/O3
A1
A0
A3
A2
109V33–3