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M59DR032EA Datasheet(PDF) 19 Page - STMicroelectronics |
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M59DR032EA Datasheet(HTML) 19 Page - STMicroelectronics |
19 / 43 page 19/43 M59DR032EA, M59DR032EB Table 12. Status Register Bits Note: 1. Logic level ’1’ is High, ’0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive read operations. 2. In case of double word program DQ7 refers to the last word input. DQ Name Logic Level Definition Note 7 Data Polling ’1’ Erase complete or erase block in Erase Suspend. Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits DQ5 for Program or Erase success. ’0’ Erase in progress DQ Program complete or data of non erase block during Erase Suspend. DQ Program in progress(2) 6 Toggle Bit ’-1-0-1-0-1-0-1-’ Erase or Program in progress Successive reads output complementary data on DQ6 while Programming or Erase operations are in progress. DQ6 remains at constant level when P/E.C. operations are completed or Erase Suspend is acknowledged. DQ Program complete ’-1-1-1-1-1-1-1-’ Erase complete or Erase Suspend on currently addressed block 5 Error Bit ’1’ Program or Erase Error This bit is set to ’1’ in the case of Programming or Erase failure. ’0’ Program or Erase in progress 4 Reserved 3 Erase Time Bit ’1’ Erase Timeout Period Expired P/E.C. Erase operation has started. Only possible command entry is Erase Suspend ’0’ Erase Timeout Period in progress An additional block to be erased in parallel can be entered to the P/E.C provided that it belongs to the same bank 2 Toggle Bit ’-1-0-1-0-1-0-1-’ Erase Suspend read in the Erase Suspended Block. Erase Error due to the currently addressed block (when DQ5 = ’1’). Indicates the erase status and allows to identify the erased block. 1 Program in progress or Erase complete. DQ Erase Suspend read on non Erase Suspend block. 1 Reserved 0 Reserved |
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