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PRELIMINARY
CYV15G0404DXB
Document #: 38-02097 Rev. **
Page 3 of 43
TXLBA
TXLBC
Transmit Path Block Diagram
TXRATEA
SPDSELA
REFCLKA+
REFCLKA–
Transmit PLL
Clock Multiplier
TXCLKA
Bit-Rate Clock
Character-Rate Clock A
OUTA1+
OUTA1–
OUTA2+
OUTA2–
8
TXRATEB
SPDSELB
REFCLKB+
REFCLKB–
Bit-Rate Clock
Character-Rate Clock B
OUTB1+
OUTB1–
OUTB2+
OUTB2–
Transmit PLL
Clock Multiplier A
TXCLKB
TXRATEC
SPDSELC
REFCLKC+
REFCLKC–
TXCLKC
Bit-Rate Clock
Character-Rate Clock C
TXRATED
SPDSELD
REFCLKD+
REFCLKD–
Transmit PLL
Clock Multiplier D
TXCLKD
Bit-Rate Clock
Character-Rate Clock D
OUTD1+
OUTD1–
OUTD2+
OUTD2–
OUTC1+
OUTC1–
OUTC2+
OUTC2–
TXCTA[1:0]
TXDD[7:0]
OEA[2..1]
TXBIST
ENCBYPA
TXCKSELA
= Internal Signal
TXERRA
TXERRB
TXERRD
TXERRC
TXCLKOA
TXCLKOB
TXCLKOC
TXCLKOD
TXDA[7:0]
2
TXDB[7:0]
8
2
TXCTB[1:0]
8
2
TXDC[7:0]
TXCTC[1:0]
8
2
TXCTD[1:0]
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
A
ENCBYPB
ENCBYPC
ENCBYPD
TXBISTB
TXBISTC
TXBISTD
OEB[2..1]
OEC[2..1]
OED[2..1]
PABRSTA
PABRSTB
PABRSTC
PABRSTD
OEA[2..1]
OEB[2..1]
OEC[2..1]
OED[2..1]
TXLBD
TXLBB
Transmit PLL
Clock Multiplier B
Transmit PLL
Clock Multiplier C
1
0
TXCKSELB
0
TXCKSELC
1
0
TXCKSELD
1
0
RECLCK[A..D] are Internal Reclocker Signals
1
RECLCKA
RECLCKB
RECLCKC
RECLCKD
TXLB[A..D] are Internal Serial Loopback Signals
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