CY7C344
Document #: 38-03006 Rev. **
Page 6 of 15
External Asynchronous Switching Characteristics Over Operating Range[7]
7C344-15
7C344-20
7C344-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tACO1
Asynchronous Clock Input to Output Delay
Com’l/Ind
15
20
25
ns
Mil
15
20
25
tACO2
Asynchronous Clock Input to Local Feedback to
Combinatorial Output[19]
Com’l/Ind
30
30
37
ns
Mil
30
30
37
tAS
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
Com’l/Ind
7
9
12
ns
Mil
7
9
12
tAH
Input Hold Time from Asynchronous Clock Input
Com’l/Ind
7
9
12
ns
Mil
7
9
12
tAWH
Asynchronous Clock Input HIGH Time[4, 20]
Com’l/Ind
6
7
9
ns
Mil
6
7
9
tAWL
Asynchronous Clock Input LOW Time[4]
Com’l/Ind
7
9
11
ns
Mil
7
9
11
tACF
Asynchronous Clock to Local Feedback Input[4, 21]
Com’l/Ind
18
18
21
ns
Mil
18
18
21
tAP
External Asynchronous Clock Period (1/fMAX4)
[4]
Com’l/Ind
13
16
20
ns
Mil
13
16
20
fMAXA1
External Maximum Frequency in Asynchronous
Mode 1/(tACO1 + tAS)
[4, 22]
Com’l/Ind
45.4
34.4
27
MHz
Mil
45.4
34.4
27
fMAXA2
Maximum Internal Asynchronous Frequency
1/(tACF + tAS) or 1/(tAWH + tAWL)
[4, 23]
Com’l/Ind
40
37
30.3
MHz
Mil
40
37
30.3
fMAXA3
Data Path Maximum Frequency in Asynchronous
Mode[4, 24]
Com’l/Ind
66.6
50
40
MHz
Mil
66.6
50
40
fMAXA4
Maximum Asynchronous Register Toggle
Frequency 1/(tAWH + tAWL)
[4, 25]
Com’l/Ind
76.9
62.5
50
MHz
Mil
76.9
62.5
50
tAOH
Output Data Stable Time from Asynchronous Clock
Input[4, 26]
Com’l/Ind
15
15
15
ns
Mil
15
15
15
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the registered output signal to a combinatorial
output for which the registered output signal is used as an input. Assumes no expanders are used in logic of combinatorial output or the asynchronous clock
input. This parameter is tested periodically by sampling production material.
20. This parameter is measured with a positive-edge-triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL.
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronously clocked register. This delay plus the
asynchronous register set-up time, tAS, is the minimum internal period for an asynchronously clocked state machine configuration. This delay assumes no expander logic
in the asynchronous clock path. This parameter is tested periodically by sampling production material.
22. This parameter indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that no expander logic is employed in the clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
If register output states must also control external points, this frequency can still be observed as long as this frequency is less than 1/tACO1. This specification
assumes no expander logic is utilized. This parameter is tested periodically by sampling production material.
24. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode. This frequency is least of 1/(tAWH + tAWL), 1/(tAS + tAH), or 1/tACO1. It also indicates the maximum frequency at which the device may operate in the asynchronously
clocked data-path mode. Assumes no expander logic is used.
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked
mode by a clock signal applied to an external dedicated input or an I/O pin.
26. This parameter indicates the minimum time that the previous register output data is maintained on the output pin after an asynchronous register clock input
to an external dedicated input or I/O pin.