SN74V263 datasheet(44/52 Pages) TI

Part #	SN74V263

Description	8192 횞 18, 16384 횞 18, 32768 횞 18, 65536 횞 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

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SN74V263, SN74V273, SN74V283, SN74V293

8192

× 18, 16384 × 18, 32768 × 18, 65536 × 18

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003

44

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

+ 1 Words in FIFO (see Note B)

WCLK

WEN

HF

RCLK

REN

D + 1

2

D/2 Words in FIFO (see Note A)

tENH

tENS

Words in FIFO (see Note B)

D

2

+ 1 Words in FIFO (see Note A)

D + 1

2

D/2 Words in FIFO (see Note A)

Words in FIFO (see Note B)

D + 1

2

tCLKL

tCLKH

tHF

NOTES: A. In standard mode: D = maximum FIFO depth. If

×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263,

D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both

×9 input and ×9 output bus

widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072

for the SN74V293.

B. In FWFT mode: D = maximum FIFO depth. If

×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263,

D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both

×9 input and ×9 output bus

widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073

for the SN74V293.

tHF

Figure 22. Half-Full Flag Timing (FWFT and Standard Modes)

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