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CY7C344
Document #: 38-03006 Rev. **
Page 7 of 15
Typical Internal Switching Characteristics Over Operating Range[7]
7C344-15
7C344-20
7C344-25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
tIN
Dedicated Input Pad and Buffer Delay
Com’l/Ind
4
5
7
ns
Mil
4
5
7
tIO
I/O Input Pad and Buffer Delay
Com’l/Ind
4
5
7
ns
Mil
4
5
7
tEXP
Expander Array Delay
Com’l/Ind
8
10
15
ns
Mil
8
10
15
tLAD
Logic Array Data Delay
Com’l/Ind
7
9
10
ns
Mil
7
9
10
tLAC
Logic Array Control Delay
Com’l/Ind
5
7
7
ns
Mil
5
7
7
tOD
Output Buffer and Pad Delay
Com’l/Ind
4
5
5
ns
Mil
4
5
5
tZX
Output Buffer Enable Delay[27]
Com’l/Ind
7
8
11
ns
Mil
7
8
11
tXZ
Output Buffer Disable Delay
Com’l/Ind
7
8
11
ns
Mil
7
8
11
tRSU
Register Set-Up Time Relative to Clock Signal
at Register
Com’l/Ind
5
5
8
ns
Mil
558
tRH
Register Hold Time Relative to Clock Signal at
Register
Com’l/Ind
7
9
12
ns
Mil
7
9
12
tLATCH
Flow-Through Latch Delay
Com’l/Ind
1
1
3
ns
Mil
1
1
3
tRD
Register Delay
Com’l/Ind
1
1
1
ns
Mil
1
1
1
tCOMB
Transparent Mode Delay[28]
Com’l/Ind
1
1
3
ns
Mil
1
1
3
tCH
Clock HIGH Time
Com’l/Ind
6
7
8
ns
Mil
678
tCL
Clock LOW Time
Com’l/Ind
6
7
8
ns
Mil
678
tIC
Asynchronous Clock Logic Delay
Com’l/Ind
7
8
10
ns
Mil
7
8
10
tICS
Synchronous Clock Delay
Com’l/Ind
1
2
3
ns
Mil
1
2
3
tFD
Feedback Delay
Com’l/Ind
1
1
1
ns
Mil
1
1
1
tPRE
Asynchronous Register Preset Time
Com’l/Ind
5
6
9
ns
Mil
5
6
9
tCLR
Asynchronous Register Clear Time
Com’l/Ind
5
6
9
ns
Mil
5
6
9
tPCW
Asynchronous Preset and Clear Pulse Width
Com’l/Ind
5
5
7
ns
Mil
557
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