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ICS9169C-231 Datasheet(PDF) 5 Page - Integrated Circuit Systems

Part No. ICS9169C-231
Description  Frequency Generator for Pentium Based Systems
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Maker  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com
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ICS9169C-231 Datasheet(HTML) 5 Page - Integrated Circuit Systems

   
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5
ICS169C-231
Technical Pin Function Descriptions
VDD1
This is the power supply to the internal logic of the device
as well as the following clock output buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. Fixed clock output buffers
This pin may be operated at any voltage between 3.0 and
5.5 volts. Clocks from the listed buffers that it supplies
will have a voltage swing from ground to this level. For the
actual guaranteed high and low voltage levels of these
clocks, please consult the AC parameter table in this data
sheet.
GND
This is the power supply ground return pin for the internal
logic of the device as well as the following clock output
buffers:
A. REF clock output buffers
B. BUS clock output buffers
C. CPU clock output buffers
X1
This pin serves one of two functions. When the device is
used with a crystal, X1 acts as the input pin for the
reference signal that comes from the discrete crystal.
When the device is driven by an external clock signal, X1
is the device’ input pin for that reference clock. This pin
also implements an internal crystal loading capacitor that
is connected to ground. See the data tables for the value of
the capacitor.
X2
This pin is used only when the device uses a Crystal as the
reference frequency source. In this mode of operation, X2
is an output signal that drives (or excites) the discrete
crystal. This pin also implements an internal crystal loading
capacitor that is connected to ground. See the data tables
for the value of the capacitor.
CPU (1:8)
This pin is the clock output that drives processor and other
CPU related circuitry that require clocks which are in tight
skew tolerance with the CPU clock. The voltage swing of
these clocks is controlled by that which is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies this clock operates at and the selection codes
that are necessary to produce these frequencies.
BUS (1:6)
This pin is the clock output that is intended to drive the
systems plug-in card bus. The voltage swing of these
clocks is controlled by the supply that is applied to the
VDD pin of the device. See the Functionality table at the
beginning of this data sheet for a list of the specific
frequencies that this clock operates at and the selection
codes that are necessary to produce these frequencies.
FS0, FS1, FS2
These pins control the frequency of the clocks at the CPU,
CPUL, BUS, SDRAM, AGP and IOAPIC pins. See the Fun-
tionality table at the beginning of this data sheet for a list
of the specific frequencies that this clock operates at and
the selection codes that are necessary to produce these
frequencies. The device reads these pins at power-up and
stores the programmed selection code in an internal data
latch. (See programming section of this data sheet for
configuration circuitry recommendations.
BSEL
When this pin is a logic 1, it will place the CPU clocks in
the synchronous mode (running at half the frequency of
the Ref). If this pin is a logic 0, it will be in the asynchronous
mode for the CPU clocks and will operate at the
preprogrammed fixed frequency rate. It is a shared pin
and is programed the same way as the Frequency Select
pins.
VDD 2, 3
These are the power supply pins for the CPU clock buffers.
By separating the clock power pins, each group can receive
the appropriate power decoupling and bypassing necessary
to minimize EMI and crosstalk between the individual
signals. VDD2 can be reduced to 2.5V VDD for advanced
processor clocks which will bring CPU (1:6) outputs at 0
to 2.5V output swings.
48 MHz
This is a fixed frequency clock that is typically used to
drive Super I/O peripheral device needs.
24 MHz
This is a fixed frequency clock that is typically used to
drive Keyboard controller clock needs.
VDD4
This power pin supplies the BUS clock buffers.
REF
This is a fixed frequency clock that runs at the same
frequency as the input reference clock (typically 14.31818
MHz) is and typically used to drive Video and ISA BUS
requirements.
VDD5
This power pin supplies the 48/24 MHz clocks.


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