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ICS9169C-231 Datasheet(PDF) 3 Page - Integrated Circuit Systems

Part No. ICS9169C-231
Description  Frequency Generator for Pentium Based Systems
Download  8 Pages
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Maker  ICST [Integrated Circuit Systems]
Homepage  http://www.icst.com

ICS9169C-231 Datasheet(HTML) 3 Page - Integrated Circuit Systems

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Fig. 1
Shared Pin Operation - Input/Output, Pins 5, 28, 12 and
13 on the ICS9169C-231 serve as dual signal functions to
the device. During initial power-up, they act as input pins.
The logic level (voltage) that is present on these pins at
this time is read and stored into a 4-bit internal data latch.
At the end of Power-On reset, (see AC characteristics for
timing values), the device changes the mode of operations
for these pins to an output function. In this mode the pins
produce the specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic
1) power supply or the GND (logic 0) voltage potential. A
10 Kilohm(10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load
on the output clock during the subsequent operating
Figs. 1 and 2 show the recommended means of
implementing this function.
In Fig. 1 either one of the
resistors is loaded onto the board (selective stuffing) to
configure the device’s internal logic. Figs. 2a and b provide
a single resistor loading option where either solder spot
tabs or a physical jumper header may be used.
These figures illustrate the optimal PCB physical layout
options. These configuration resistors are of such a large
ohmic value that they do not effect the low impedance
clock signals. The layouts have been optimized to provide
as little impedance transition to the clock signal as possible,
as it passes through the programming resistor pad(s).
Shared Pin Operation -
Input/Output Pins
The ICS9169C-231 includes a production test verification
mode of operation. This requires that the FS0 and FS1 pins
be programmed to a logic high and the FS2 pin be
programmed to a
logic low(see
Shared Pin Operation
section). In this mode the device will output the following
Note: REF is the frequency of either the crystal connected
between the devices X1and X2 or, in the case of a device
being driven by an external reference clock, the frequency
of the reference (or test) clock on the device’s X1 pin.
Test Mode Operation
CPU (1:8)
BUS (1:6)

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