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TC7MZ273FK Datasheet(PDF) 4 Page - Toshiba Semiconductor

Part No. TC7MZ273FK
Description  Low-Voltage Octal D-Type Flip-Flop with Clear with 5-V Tolerant Inputs and Outputs
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Maker  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC7MZ273FK Datasheet(HTML) 4 Page - Toshiba Semiconductor

   
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TC7MZ273FK
2001-10-23
4
Electrical Characteristics
DC Characteristics (Ta
==== −−−−40~85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
High level
VIH
2.7~3.6
2.0
Input voltage
Low level
VIL
2.7~3.6
0.8
V
IOH = −100 µA
2.7~3.6
VCC
− 0.2
IOH = −12 mA
2.7
2.2
IOH = −18 mA
3.0
2.4
High level
VOH
VIN = VIH or VIL
IOH = −24 mA
3.0
2.2
IOL = 100 µA
2.7~3.6
0.2
IOL = 12 mA
2.7
0.4
IOL = 16 mA
3.0
0.4
Output voltage
Low level
VOL
VIN = VIH or VIL
IOL = 24 mA
3.0
0.55
V
Input leakage current
IIN
VIN = 0~5.5 V
2.7~3.6
±5.0
µA
Power off leakage current
IOFF
VIN/VOUT = 5.5 V
0
10.0
µA
VIN = VCC or GND
2.7~3.6
10.0
Quiescent supply current
ICC
VIN = 3.6~5.5 V
2.7~3.6
±10.0
Increase in ICC per input
∆ICC
VIN = VCC − 0.6 V
2.7~3.6
500
µA
AC Characteristics (Ta
==== −−−−40~85°C)
Characteristics
Symbol
Test Condition
VCC (V)
Min
Max
Unit
2.7
Maximum clock frequency
fMAX
Figure 1, Figure 2
3.3
± 0.3
150
MHz
2.7
9.5
Propagation delay time (CK-Q)
tPLH
tPHL
Figure 1, Figure 2
3.3
± 0.3
1.5
8.5
ns
2.7
9.5
Propagation delay time ( CLR -Q)
tPHL
Figure 1, Figure 3
3.3
± 0.3
1.5
8.5
ns
2.7
3.3
Minimum pulse width (CK)
tw (H)
tw (L)
Figure 1, Figure 2
3.3
± 0.3
3.3
ns
2.7
3.3
Minimum bus width ( CLR )
tw (L)
Figure 3
3.3
± 0.3
3.3
ns
2.7
2.5
Minimum set-up time
ts
Figure 1, Figure 2
3.3
± 0.3
2.5
ns
2.7
1.5
Minimum hold time
th
Figure 1, Figure 2
3.3
± 0.3
1.5
ns
2.7
2.5
Minimum removal time
trem
Figure 4
3.3
± 0.3
2.0
ns
2.7
Output to output skew
tosLH
tosHL
(Note10)
3.3
± 0.3
1.0
ns
Note10: This parameter is guaranteed by design.
(tosLH = |tpLHm − tpLHn|, tosHL = |tpHLm − tpHLn|)


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