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NCP3163PWR2G Datasheet(PDF) 8 Page - ON Semiconductor |
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NCP3163PWR2G Datasheet(HTML) 8 Page - ON Semiconductor |
8 / 20 page NCP3163 http://onsemi.com 8 INTRODUCTION The NCP3163 is a monolithic power switching regulator optimized for DC−to−DC converter applications. The combination of its features enables the system designer to directly implement step−up, step−down, and voltage− inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. A representative block diagram is shown in Figure 2. OPERATING DESCRIPTION The NCP3163 operates as a fixed on−time, variable off−time voltage mode ripple regulator. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 19. The output voltage waveform shown is for a step−down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the feedback comparator sets the latch, immediately terminating switch conduction. The feedback comparator will inhibit the switch until the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be inhibited for a partial oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. Oscillator The oscillator frequency and on−time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 9 to 1 ratio internal current source and sink, generating a negative going sawtooth waveform at Pin 6. As CT charges, an internal pulse is generated at the oscillator output. This pulse is connected to the NOR gate center input, preventing output switch conduction, and to the AND gate upper input, allowing the latch to be reset if the comparator output is low. Thus, the output switch is always disabled during ramp−up and can be enabled by the comparator output only at the start of ramp−down. The oscillator peak and valley thresholds are 1.25 V and 0.55 V, respectively, with a charge current of 225 mA and a discharge current of 25 mA, yielding a maximum on−time duty cycle of 90%. A reduction of the maximum duty cycle may be required for specific converter configurations. This can be accomplished with the addition of an external deadtime resistor (RDT) placed across CT. The resistor increases the discharge current which reduces the on−time of the output switch. The converter output can be inhibited by clamping CT to ground with an external NPN small−signal transistor. To calculate the frequency when only CT is connected to Pin 6, use the equations found in Figure 22. When RT is also used, the frequency and maximum duty cycle can be calculated with the NCP3163 design tool found at www.onsemi.com. Comparator Output Timing Capacitor CT Oscillator Output Output Switch Output Voltage Nominal Output Voltage Level 1 0 1.25 V 0.55 V 1 0 On Off Figure 19. Typical Operating Waveforms Startup Quiescent Operation 9t t |
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