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74LVC74A Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LVC74A
Description  Dual D-type flip-flop with set and reset; positive-edge trigger
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LVC74A Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product Specification
74LVC74A
Dual D-type flip-flop with set and reset;
positive-edge trigger
2
1998 Jun 17
853-2070 19589
FEATURES
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with JEDEC standard no. 8-1A.
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50 W transmission lines @ 85°C
DESCRIPTION
The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.
The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 50 pF;
VCC = 3.3 V
3.6
3.5
3.5
ns
fmax
Maximum clock frequency
250
MHz
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per flip-flop
Notes 1 and 2
30
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) + (VO2/RL) × duty factor LOW, where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
14-Pin Plastic SO
–40
°C to +85°C
74LVC74A D
74LVC74A D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +85°C
74LVC74A DB
74LVC74A DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +85°C
74LVC74A PW
74LVC74APW DH
SOT402-1
PIN CONFIGURATION
SV00491
1RD
1D
1CP
1SD
1Q
1Q
GND
VCC
2RD
2D
2CP
2SD
2Q
2Q
1
2
3
4
5
6
78
9
10
11
12
13
14
LOGIC SYMBOL (IEEE/IEC)
SV00332
4
3
2
1
10
11
12
13
5
6
9
8
S
C1
1D
R
S
C2
2D
R


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