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74LVC273 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LVC273
Description  Octal D-type flip-flop with reset; positive-edge trigger
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LVC273 Datasheet(HTML) 2 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
2
1998 May 20
853-2064 19419
FEATURES
Wide supply voltage range of 1.2V to 3.6V
Conforms to JEDEC standard 8-1A
Inputs accept voltages up to 5.5V
CMOS low power consumption
Direct interface with TTL levels
Output drive capability 50Ω transmission lines @ 85°C
DESCRIPTION
The 74LVC273 is a low-voltage Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC273 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. The common clock (CP) and
master reset (MR) inputs load and reset (clear) all flip-flops
simultaneously. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition, is transferred to the
corresponding output (Qn) of the flip-flop.
All outputs will be forced LOW independently of clock or data inputs
by a LOW voltage level on the MR input.
The device is useful for applications where the true output only is
required and the clock and master reset are common to all storage
elements.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
CP to Qn;
MR to Qn
CL = 50pF
VCC = 3.3V
6.0
6.0
ns
f
Maximum clock frequency
230
MHz
fmax
Maximum clock frequency
230
MHz
CI
Input capacitance
5.0
pF
CPD
Power dissipation
capacitance per flip-flop
VI = GND to VCC1
22
pF
NOTE:
1CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
20-Pin Plastic SO
–40
°C to +85°C
74LVC273 D
74LVC273 D
SOT163-1
20-Pin Plastic SSOP Type II
–40
°C to +85°C
74LVC273 DB
74LVC273 DB
SOT339-1
20-Pin Plastic TSSOP Type I
–40
°C to +85°C
74LVC273 PW
74LVC273PW DH
SOT360-1
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
VCC
15
16
17
18
19
20
MR
Q0
D0
D1
Q1
Q2
D2
D3
Q3
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
SY00051
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1
MR
Master reset input (active LOW)
2, 5, 6,
9, 12, 15,
16, 19
Q0 – Q7
Flip-flop outputs
3, 4, 7,
8, 13, 14,
17, 18
D0 – D7
Data inputs
10
GND
Ground (0V)
11
CP
Clock input (LOW-to-HIGH,
edge-triggered)
20
VCC
Positive power supply


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