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74LVC273 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. 74LVC273
Description  Octal D-type flip-flop with reset; positive-edge trigger
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LVC273 Datasheet(HTML) 5 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LVC273
Octal D-type flip-flop with reset; positive-edge trigger
1998 May 20
5
AC CHARACTERISTICS
GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; Tamb = –40°C to +85°C.
LIMITS
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
VCC = 2.7V
UNIT
MIN
TYP1
MAX
MIN
TYP
MAX
tPHL
tPLH
Propagation delay
CP to Qn
1
6.0
10.2
6.6
11.2
ns
tPHL
Propagation delay
MR to Qn
2
6.3
11.0
7.4
12.0
ns
tW
Clock pulse width
HIGH or LOW
1
4
1.2
5
1.8
ns
tW
Master reset pulse
width LOW
2
4
1.2
5
1.7
ns
trem
Removal time
MR to CP
2
2
–1.0
3
–1.0
ns
tsu
Set-up time
Dn to CP
3
2
0.7
3
1.0
ns
th
Hold time
Dn to CP
3
0
–0.6
0
–0.9
ns
fmax
Maximum clock
pulse frequency
1
125
100
MHz
NOTE:
1. These typical values are at VCC = 3.3V and Tamb = 25°C.
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V.
VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VM
VM
1/fMAX
tw
tPHL
tPLH
CP INPUT
Qn OUTPUT
SW00078
GND
VOH
VOL
VI
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
VM
MR INPUT
Qn OUTPUT
tw
tPHL
trem
CP INPUT
SY00053
VCC
GND
VCC
GND
VOH
VOL
VM
VM
VM
Waveform 2. Master reset (MR) pulse width, the master reset to
output (Qn) propagation delays and the master reset to clock
(CP) removal time
VM
SW00079
VI
GND
VM
Dn
INPUT
VI
GND
VM
VOH
Qn
OUTPUT
VOL
CP
INPUT
tsu
th
tsu
th
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 3. Data set-up and hold times for the data input (Dn)


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