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74LVC2373A Datasheet(PDF) 3 Page - NXP Semiconductors

Part No. 74LVC2373A
Description  Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor 3-State
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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74LVC2373A Datasheet(HTML) 3 Page - NXP Semiconductors

 
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Philips Semiconductors
Product specification
74LVC2373A
74LVCH2373A
Octal D-type transparent latch with 5-volt tolerant
inputs/outputs; damping resistor (3-State)
1997 Mar 12
3
PIN CONFIGURATION
SV00657
Q0
Q1
Q2
Q3
GND
Q4
Q5
Q6
Q7
D0
D1
D2
D3
VCC
D4
D5
D6
D7
LE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
1
OE
Output enable input (active LOW)
2, 5, 6, 9, 12,
15, 16, 19
Q0–Q7
3-State latch outputs
3, 4, 7, 8, 13,
14, 17, 18
D0–D7
Data inputs
10
GND
Ground (0V)
11
LE
Latch enable input (active HIGH)
20
VCC
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
SV00659
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
C1
EN1
1D
11
1
LOGIC SYMBOL
SV00658
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
LE
2
5
6
9
12
15
16
19
11
3
4
7
8
13
14
17
18
1
OE
FUNCTIONAL DIAGRAM
SV00660
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
LE
1
LATCH
1 to 8
3–STATE
OUTPUTS
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
OE
FUNCTION TABLE
OPERATING
INPUTS
INTERNAL
OUTPUTS
MODES
OE
LE
Dn
LATCHES
Q0 to Q7
Enable and
read register
(transparent
mode)
L
L
H
H
L
H
L
H
L
H
Latch and read
register
L
L
L
L
I
h
L
H
L
H
Latch register
and disable
outputs
H
H
L
L
I
h
L
H
Z
Z
H = HIGH voltage level
h
= HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L
= LOW voltage level
I
= LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
X = Don’t care
Z = High impedance OFF-state


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