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74LVC162244A Datasheet(PDF) 2 Page - NXP Semiconductors |
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74LVC162244A Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 10 page  2003 Dec 12 2 Philips Semiconductors Product specification 16-bit buffer/line driver, 30 Ω series termination resistors; 5 V tolerant input/output; 3-state 74LVC162244A; 74LVCH162244A FEATURES • 5 V tolerant inputs/outputs for interfacing with 5 V logic • Wide supply voltage range from 1.2 to 3.6 V • CMOS low power consumption • MULTIBYTE flow-through standard pin-out architecture • Low inductance multiple power and ground pins for minimum noise and ground bounce • Direct interface with TTL levels • Inputs accept voltages up to 5.5 V • Integrated 30 Ω termination resistors • All data inputs have bushold (74LVCH162244A only) • Complies with JEDEC standard no. 8-1A • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. • Specified from −40 to +85 °C and −40 to +125 °C. DESCRIPTION The 74LVC(H)162244A is a high-performance, low power, low voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices as a mixed 3.3 and 5 V environment. The 74LVC(H)162244A is a 16-bit non-inverting buffer/line driver with 3-state outputs. The device can be used as four 4-bit buffers, two 8-bit buffers or one 16-bit buffer. The 3-state outputs are controlled by the output enable inputs 1OE, 2OE, 3OE and 4OE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. The 74LVCH162244A bushold data inputs eliminates the need for external termination resistors to hold unused inputs. The 74LVC(H)162244A is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce line noise. QUICK REFERENCE DATA GND = 0 V; Tamb =25 °C; tr =tf ≤ 2.5 ns. Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; Σ(CL × VCC2 × fo) = sum of the outputs. 2. The condition is VI = GND to VCC. SYMBOL PARAMETER CONDITIONS TYPICAL UNIT tPHL/tPLH propagation delay nAn to nYn CL = 50 pF; VCC = 3.3 V 3.0 ns tPZH/tPZL 3-state output enable time nOE to nYn CL = 50 pF; VCC = 3.3 V 3.5 ns tPHZ/tPLZ 3-state output disable time nOE to nYn CL = 50 pF; VCC = 3.3 V 2.8 ns CI input capacitance 5.0 pF CPD power dissipation capacitance per gate VCC = 3.3 V; notes 1 and 2 outputs enabled 12 pF outputs disabled 4.0 pF |
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