Philips Semiconductors

Product data sheet

SSTVF16859

13-bit 1:2 SSTL_2 registered buffer for DDR

2

2004 Jul 12

FEATURES

applications

Protection exceeds 2000 V to HBM per method A114.

exceeds 100 mA.

HVQFN packages

DESCRIPTION

The SSTVF16859 is a 13-bit to 26-bit SSTL_2 registered driver with

differential clock inputs, designed to operate between 2.3 V and

2.7 V for PC1600 – PC2700 applications or between 2.5 V and 2.7 V

for PC3200 applications. All inputs are compatible with the JEDEC

LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II

compatible which can be used for standard stub-series applications

or capacitive loads. Master reset (RESET) asynchronously resets all

registers to zero.

The SSTVF16859 is intended to be incorporated into standard

DIMM (Dual In-Line Memory Module) designs defined by JEDEC,

such as DDR (Double Data Rate) SDRAM and SDRAM II Memory

Modules. Different from traditional SDRAM, DDR SDRAM transfers

data on both clock edges (rising and falling), thus doubling the peak

bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst

rate of 266 MHz.

The device data inputs consist of different receivers. One differential

input is tied to the input pin while the other is tied to a reference

input pad, which is shared by all inputs.

The clock input is fully differential (CK and CK) to be compatible with

DRAM devices that are installed on the DIMM. Data are registered

at the crossing of CK going HIGH, and CK going LOW. However,

since the control inputs to the SDRAM change at only half the data

rate, the device must only change state on the positive transition of

the CK signal. In order to be able to provide defined outputs from the

device even before a stable clock has been supplied, the device has

an asynchronous input pin (RESET), which when held to the LOW

state, resets all registers and all outputs to the LOW state.

The device supports low-power standby operation. When RESET is

LOW, the differential input receivers are disabled, and undriven

allowed. In addition, when RESET is LOW, all registers are reset,

and all outputs are forced LOW. The LVCMOS RESET input must

always be held at a valid logic HIGH or LOW level.

To ensure defined outputs from the register before a stable clock

has been supplied, RESET must be held in the LOW state during

power-up.

In the DDR DIMM application, RESET is specified to be completely

asynchronous with respect to CK and CK. Therefore, no timing

relationship can be guaranteed between the two. When entering

RESET, the register will be cleared and the outputs will be driven

LOW. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW-to-HIGH transition of RESET until the

input receivers are fully enabled, the outputs will remain LOW.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

Propagation delay; CLK to Qn

1.7

ns

Input capacitance

2.8

pF

NOTE:

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

DWG NUMBER

56-Terminal Plastic HVQFN

0

°C to +70 °C

SSTVF16859BS

SOT684-1

64-Pin Plastic TSSOP

0

°C to +70 °C

SSTVF16859DGG

SOT646-1

96-Ball Plastic LFBGA

0

°C to +70 °C

SSTVF16859EC

SOT536-1