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IDT72V8988 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT72V8988
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V8988 Datasheet(HTML) 5 Page - Integrated Device Technology

 
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Commercial Temperature Range
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
TABLE 1
 VARIABLE DELAY MODE
Theinformationswitchedtothethirdtimeslotaftertheinputhasenteredthe
device (for instance, input channel 0 to output channel 3 or input channel 30 to
output channel 1), will always appear on the output three channels later in the
sameincomingframe.
Any switching configuration that provides three or more time slots between
input and output channels, will have a throughput delay equal to the difference
between the output and input channels; i.e., the throughput delay will be less
thanoneframe. Table1showsthepossibledelaysfortheIDT72V8988device
in Variable Delay Mode. An example is shown in Figure 3.
CONSTANT DELAY MODE
In this mode frame integrity is maintained in all switching configurations by
making use of a multiple Data Memory buffer technique where input channels
written in any of the buffers during frame N will be read out during frame N+2.
In the IDT72V8988, the minimum throughput delay achievable in Constant
Delay mode will be 32 time slots; for example, when input time slot 32 (channel
31) is switched to output time slot 1 (channel 0). Likewise, the maximum delay
is achieved when the first time slot in a frame (channel 0) is switched to the last
time slot in the frame (channel 31), resulting in 94 time slots of delay (see
Figure 4).
Tosummarize,anyinputtimeslotfrominputframeNwillbealwaysswitched
to the destination time slot on output frame N+2. In Constant Delay mode the
device throughput delay is calculated according to the following formula:
DELAY=[32+(32-IN)+(OUT-1)]
IN =the number of the input time slot (from 1 to 32)
OUT = the number of the output time slot (from 1 to 32).
MICROPROCESSOR PORT
The IDT72V8988 microprocessor port is a non-multiplexed bus architec-
ture. Theparallelportconsistsofan8-bitparalleldatabus(D0-D7),sixaddress
input lines (A0-A5) and four control lines (
CS,DS,R/WandDTA). Thisparallel
microportallowstheaccesstotheControlRegisters,ConnectionMemoryLow,
Connection Memory High, and the Data Memory. All locations are read/write
access able except for the Data Memory, which can be read only.
Accesses from the microport to the Connection Memory and the Data
Memory are multiplexed with accesses from the input and output TDM ports.
This can cause variable Data Acknowledge delays (
DTA). IntheIDT72V8988
device, the
DTAoutputprovidesamaximumacknowledgmentdelayof800ns
for read/write operations in the Connection Memory. However, for operations
in the Data Memory (Processor Mode), the maximum acknowledgment delay
can be 1220ns.
SOFTWARE CONTROL
IftheA5,A1,A0addresslineinputsareLOWthentheIDT72V8988Internal
Control Register is addressed (see Table 2). If A5 input line is high, then the
remaining address input lines are used to select the 32 possible channels per
input or output stream. As explained in the Control Register description, the
address input lines and the Stream Address bits (STA) of the Control register
give the user the capability of selecting all positions of IDT72V8988 Data and
Connect memories. See Figure 6 for accessing internal memories.
The data in the control register consists of Memory Select and Stream
Addressbits,SplitMemoryandProcessorEnablebits(Table3).InSplitMemory
mode (Bit 7 of the Control register) reads are from the Data Memory and writes
are to the Connection Memory LOW. The Memory Select bits allow the
Connection Memory High or LOW or the Data Memory to be chosen, and the
StreamAddressbitsdefineinternalmemorysubsectionscorrespondingtoinput
or output streams.
The Processor Enable bit (bit 6) places every output channel on every
output stream in Processor Mode; i.e., the contents of the Connection Memory
LOW(CML,Table5)areoutputontheoutputstreamsonceeveryframeunless
the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8988 behaves as
if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory
High(CMH,Table4)locationsweresettoHIGH,regardlessoftheactualvalue.
IfPEisLOW,thenbit2and0ofeachConnectionMemoryHighlocationoperates
normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output
channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of
theCMLdefinethesourceinformation(streamandchannel)ofthetimeslotthat
is to be switched to an output.
If the ODE input pin is LOW, then all the serial outputs are high-impedance.
IfODEisHIGH,thenbit0(OutputEnable)oftheCMHlocationenables(ifHIGH)
or disables (if LOW) for that particular channel.
INITIALIZATION
Duringthemicroprocessorinitializationroutine,themicroprocessorshould
programthedesiredactivepathsthroughthematrices,andputallotherchannels
intothehighimpedancestate. CareshouldbetakenthatnotwoConnectedTX
outputsdrivethebussimultaneously. WiththeCMHsetup,themicroprocessor
controlling the matrices can bring the ODE signal high to relinquish high
impedance state control to the Connection Memory High bits outputs.
As the connection memory can be in any state after a power up, the ODE
pin should be used to hold the TX streams in high-impedance until the per-
channel output enable control in the connection memory high is appropriately
programmed.
Input Channel
Output Channel
Throughput Delay
n
m=n, n+1 or n+2
m-n+32 time slot
n
m>n+2
m-n time slot
n
m<n
32-(n-m) time slot
TABLE 2
 ADDRESS MAPPING
A5
A4
A3
A2
A1
A0
LOCATION
0
X
X
X
0
0
Control Register
1
00000
Channel 0
1
00001
Channel 1
1
•••••
1
•••••
1
•••••
1
•••••
1
•••••
1
11111
Channel 31


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