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IDT72V8988 Datasheet(PDF) 4 Page - Integrated Device Technology

Part No. IDT72V8988
Description  3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT72V8988 Datasheet(HTML) 4 Page - Integrated Device Technology

 
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Commercial Temperature Range
IDT72V8988 3.3V Time Slot Interchange
Digital Switch 128 x 128
5704 drw06
TX
Microprocessor
Receive
Serial Data
Streams
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Receive
Serial Data
Streams
5704 drw05
RX
TX
Transmit
Serial Data
Streams
Data
Memory
Connection
Memory
Figure 2. Processor Mode
Figure 1. Connection Mode
four output (TX0-3) serial streams are provided in the IDT72V8988 device
allowing a complete 128 x 128 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.
The received serial data is internally converted to parallel by the on chip
serial-to-parallel converters and stored sequentially in a 128-position Data
Memory.Byusinganinternalcounterthatisresetbytheinput8KHzframepulse,
F0i,theincomingserialdatastreamscanbeframedandsequentiallyaddressed.
Dependingonthetypeofinformationtobeswitched,theIDT72V8988device
can be programmed to perform time slot interchange functions with different
throughput delay capabilities on a per-channel basis. The Variable Delay
mode, most commonly used for voice applications, can be selected ensuring
minimum throughput delay between input and output data. In Constant Delay
mode,usedinmultipleorgroupedchanneldataapplications,theintegrityofthe
information through the switch is maintained.
CONNECTION MEMORY
Data to be output on the serial streams may come from two sources: Data
Memory or Connection Memory. The Connection Memory is split into HIGH
andLOWpartsandisassociatedwithparticularTXoutputstreams. InProcessor
Mode,dataoutputontheTXstreamsistakenfromtheConnectionMemoryLow
and originates from the microprocessor (Figure 2). Where as in Connection
Mode (Figure 1), data is read from Data Memory and originated from the
incomingRXstreams. Datadestinedforaparticularchannelontheserialoutput
stream is read internally during the previous channel time slot to allow time for
memory access and internal parallel-to-serial conversion.
CONNECTION MODE
In Connection Mode, the addresses of input source for all output channels
are stored in the Connection Memory Low. The Connection Memory Low
locationsaremappedtocorresponding8-bitx32-channeloutput. Thecontents
oftheDataMemoryattheselectedaddressarethentransferredtotheparallel-
to-serialconvertersbeforebeingoutput. Byhavingtheoutputchanneltospecify
theinputchannelthroughtheConnectionMemory,thesameinputchannelcan
be broadcast to several output channels.
PROCESSOR MODE
In Processor Mode the CPU writes data to the Connection Memory Low
locationswhichcorrespondtotheoutputlinkandchannelnumber. Thecontents
of the Connection Memory Low are transferred to the parallel-to-serial
converter one channel before it is to be output and are transmitted each frame
to the output until it is changed by the CPU.
CONTROL
The Connection Memory High bits (Table 4) control the per-channel
functions available in the IDT72V8988. Output channels are selected into
specific modes such as: Processor Mode or Connection mode, Variable or
Constant throughput delay modes, Output Drivers Enabled or in three-state
condition.
OUTPUT DRIVE ENABLE (ODE)
The ODE pin is the master output three-state control pin. If the ODE input
is held LOW all TDM (Time Division Multiplexed) outputs will be placed in high
impedance regardless Connection Memory High programming. However, if
ODEisHIGH,thecontentsofConnectionMemoryHighcontroltheoutputstate
on a per-channel basis.
SERIAL INTERFACE TIMING
TheIDT72V8988masterclock(
C4i)is4.096MHzsignalallowingserialdata
link configuration at 2.048 Mb/s to be implemented. The IDT72V8988 can
automatically detect the presence of an input frame pulse, identify the type of
backplanepresentontheserialinterface,andformatthesynchronizationpulse
according to ST-BUS® or GCI interface specifications (active HIGH in GCI or
active LOW in ST-BUS®). Upon determining the correct interface Connected
to the serial port, the internal timing unit establishes the appropriate serial data
bittransmitandsamplingedges. InST-BUS® mode,everysecondfallingedge
of the 4.096 MHz clock marks a boundary and the input data is clocked in by
the rising edge, three quarters of the way into the bit cell. In GCI mode every
second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit
boundaries.
DELAY THROUGH THE IDT72V8988
The transfer of information from the input serial streams to the output serial
streams results in a delay through the device. The delay through the
IDT72V8988 device varies according to the mode selected in the
V/Cbitofthe
Connection Memory High.
VARIABLE DELAY MODE
The delay in Variable Delay Mode is dependent only on the combination
ofsourceanddestinationontheinputandoutputstreams. Theminimumdelay
achievable in the IDT72V8988 device is three time slots. In the IDT72V8988
device, the information that is to be output in the same channel position as the
information is input (position n), relative to frame pulse, will be output in the
following frame (channel n, frame n+1). The same occurs if the input channels
succeeding (n+1, n+2) the channel position as the information is input.
FUNCTIONAL DESCRIPTION (Cont'd)


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