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74LV74 Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. 74LV74
Description  Dual D-type flip-flop with set and reset; positive-edge trigger
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV74 Datasheet(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
2
1998 Apr 20
853-1888 19258
FEATURES
Wide operating voltage: 1.0 to 5.5V
Optimized for Low Voltage applications: 1.0 to 3.6V
Accepts TTL input levels between V
CC = 2.7V and VCC = 3.6V
Typical V
OLP (output ground bounce) t 0.8V @ VCC = 3.3V,
Tamb = 25°C
Typical V
OHV (output VOH undershoot) u 2V @ VCC = 3.3V,
Tamb = 25°C
Output capability: standard
I
CC category: flip-flops
DESCRIPTION
The 74LV74 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT74.
The 74LV74 is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (SD) and (RD)
inputs; also complementary Q and Q outputs.
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0V; Tamb = 25°C; tr =tf v2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
CL = 15pF
VCC = 3.3V
11
14
14
ns
fmax
Maximum clock frequency
CL = 15pF
VCC = 3.3V
76
MHz
CI
Input capacitance
3.5
pF
CPD
Power dissipation capacitance per flip-flop
Notes 1 and 2
24
pF
NOTES:
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD
VCC2 x fi )S (CL
VCC2
fo) where:
fi = input frequency in MHz; CL = output load capacitance in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
S (CL
VCC2
fo) = sum of the outputs.
2. The condition is VI = GND to VCC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
14-Pin Plastic DIL
–40
°C to +125°C
74LV74 N
74LV74 N
SOT27-1
14-Pin Plastic SO
–40
°C to +125°C
74LV74 D
74LV74 D
SOT108-1
14-Pin Plastic SSOP Type II
–40
°C to +125°C
74LV74 DB
74LV74 DB
SOT337-1
14-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LV74 PW
74LV74PW DH
SOT402-1
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
FUNCTION
1, 13
1RD, 2RD
Asynchronous reset-direct input
(active-LOW)
2, 12
1D, 2D
Data inputs
3, 11
1CP, 2CP
Clock input (LOW-to-HIGH),
edge-triggered)
4, 10
1SD, 2SD
Asynchronous set-direct input
(active-LOW)
5, 9
1Q, 2Q
True flip-flop outputs
6, 8
1Q, 2Q
Complement flip-flop outputs
7
GND
Ground (0V)
14
VCC
Positive supply voltage
FUNCTION TABLE
INPUTS
OUTPUTS
SD
RD
CP
D
Q
Q
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
INPUTS
OUTPUTS
SD
RD
CP
D
Qn+1
Qn+1
H
H
H
H
°
°
L
H
L
H
H
L
H
= HIGH voltage level
L
= LOW voltage level
X
= don’t care
°
= LOW-to-HIGH CP transition
Qn+1 = state after the next LOW-to-HIGH CP transition


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