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74LV74 Datasheet(PDF) 6 Page - NXP Semiconductors

Part No. 74LV74
Description  Dual D-type flip-flop with set and reset; positive-edge trigger
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74LV74 Datasheet(HTML) 6 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
74LV74
Dual D-type flip-flop with set and reset;
positive edge-trigger
1998 Apr 20
6
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
PARAMETER
WAVEFORM
CONDITION
LIMITS
–40 to +85
°C
LIMITS
–40 to +125
°C
UNIT
VCC(V)
MIN
TYP1
MAX
MIN
MAX
1.2
70
Propagation delay
2.0
24
44
56
tPHL/tPLH
Propagation delay
nCP to nQ, nQ
Figures, 1, 3
2.7
18
28
41
ns
nCP to nQ, nQ
3.0 to 3.6
132
26
33
4.5 to 5.5
9.53
17
23
1.2
90
Propagation delay
2.0
31
46
58
tPHL/tPLH
Propagation delay
nSD to nQ, nQ
Figures 2, 3
2.7
23
34
43
ns
nSD to nQ, nQ
3.0 to 3.6
172
27
34
4.5 to 5.5
123
19
24
1.2
90
Propagation delay
2.0
31
46
58
tPHL/tPLH
Propagation delay
nRD to nQ, nQ
Figures 2, 3
2.7
23
34
43
ns
nRD to nQ, nQ
3.0 to 3.6
172
27
34
4.5 to 5.5
123
19
24
2.0
34
10
41
tW
Clock pulse width
Figure 1
2.7
25
8
30
ns
tW
HIGH to LOW
Figure 1
3.0 to 3.6
20
72
24
ns
4.5 to 5.5
15
63
18
2.0
34
10
41
tW
Set or reset pulse
Figure 2
2.7
25
8
30
ns
tW
width LOW
Figure 2
3.0 to 3.6
20
72
24
ns
4.5 to 5.5
15
63
18
1.2
5
Removal time
2.0
14
2
15
trem
Removal time
set or reset
Figure 2
2.7
10
1
11
ns
set or reset
3.0 to 3.6
8
12
9
4.5 to 5.5
6
13
7
1.2
10
Set up time
2.0
22
4
26
tsu
Set-up time
nD to nCP
Figure 1
2.7
12
3
15
ns
nD to nCP
3.0 to 3.6
8
22
10
4.5 to 5.5
6
12
8
1.2
–10
Hold time
2.0
3
–2
3
th
Hold time
nD to nCP
Figure 1
2.7
3
–2
3
ns
nD to nCP
3.0 to 3.6
3
–22
3
4.5 to 5.5
3
–23
3
2.0
14
40
12
f
Maximum clock
Figure 1
2.7
50
90
40
MHz
fmax
pulse frequency
Figure 1
3.0 to 3.6
60
1002
48
MHz
4.5 to 5.5
70
1103
56
NOTE:
1. Unless otherwise stated, all typical values are at Tamb = 25°C.
2. Typical value measured at VCC = 3.3V.
3. Typical value measured at VCC = 5.0V.


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