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LTC2291UP Datasheet(PDF) 21 Page - Linear Technology

Part # LTC2291UP
Description  Dual 12-Bit, 65/40/25Msps Low Power 3V ADCs
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC2291UP Datasheet(HTML) 21 Page - Linear Technology

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LTC2293/LTC2292/LTC2291
21
229321f
between the digital outputs and sensitive input circuitry.
The output should be buffered with a device such as an
ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Data Format
Using the MODE pin, the LTC2293/LTC2292/LTC2291
parallel digital output can be selected for offset binary or
2’s complement format. Note that MODE controls both
Channel A and Channel B. Connecting MODE to GND or
1/3VDD selects straight binary output format. Connecting
MODE to 2/3VDD or VDD selects 2’s complement output
format. An external resistor divider can be used to set the
1/3VDD or 2/3VDD logic values. Table 1 shows the logic
states for the MODE pin.
APPLICATIO S I FOR ATIO
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example, if the converter is driving a DSP powered by a 1.8V
supply, then OVDD should be tied to that same 1.8V supply.
OVDD can be powered with any voltage from 500mV up to
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OVDD. The logic outputs will
swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity. Channels A and B have independent
output enable pins (OEA, OEB).
Table 1. MODE Pin Function
Clock Duty
MODE Pin
Output Format
Cycle Stabilizer
0
Straight Binary
Off
1/3VDD
Straight Binary
On
2/3VDD
2’s Complement
On
VDD
2’s Complement
Off
Figure 12. Digital Output Buffer
229321 F12
OVDD
VDD
VDD
0.1µF
43Ω
TYPICAL
DATA
OUTPUT
OGND
OVDD
0.5V
TO VDD
PREDRIVER
LOGIC
DATA
FROM
LATCH
OE
LTC2293/LTC2292/LTC2291


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