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LTC2293 Datasheet(PDF) 20 Page - Linear Technology |
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LTC2293 Datasheet(HTML) 20 Page - Linear Technology |
20 / 28 page LTC2293/LTC2292/LTC2291 20 229321f APPLICATIO S I FOR ATIO The noise performance of the LTC2293/LTC2292/LTC2291 can depend on the clock signal quality as much as on the analog input. Any noise present on the clock signal will result in additional aperture jitter that will be RMS summed with the inherent ADC aperture jitter. In applications where jitter is critical, such as when digitiz- ing high input frequencies, use as large an amplitude as possible. Also, if the ADC is clocked with a sinusoidal signal, filter the CLK signal to reduce wideband noise and distortion products generated by the source. It is recommended that CLKA and CLKB are shorted together and driven by the same clock source. If a small time delay is desired between when the two channels sample the analog inputs, CLKA and CLKB can be driven by two different signals. If this delay exceeds 1ns, the performance of the part may degrade. CLKA and CLKB should not be driven by asynchronous signals. Maximum and Minimum Conversion Rates The maximum conversion rate for the LTC2293/LTC2292/ LTC2291 is 65Msps (LTC2293), 40Msps (LTC2292), and 25Msps (LTC2291). For the ADC to operate properly, the CLK signal should have a 50% (±5%) duty cycle. Each half cycle must have at least 7.3ns (LTC2293), 11.8ns (LTC2292), and 18.9ns (LTC2291) for the ADC internal circuitry to have enough settling time for proper operation. An optional clock duty cycle stabilizer circuit can be used if the input clock has a non 50% duty cycle. This circuit uses the rising edge of the CLK pin to sample the analog input. The falling edge of CLK is ignored and the internal falling edge is generated by a phase-locked loop. The input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. If the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3VDD or 2/3VDD using external resistors. The MODE pin controls both Channel A and Channel B—the duty cycle stabilizer is either on or off for both channels. The lower limit of the LTC2293/LTC2292/LTC2291 sample rate is determined by droop of the sample-and-hold cir- cuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junc- tion leakage will discharge the capacitors. The specified minimum operating frequency for the LTC2293/LTC2292/ LTC2291 is 1Msps. DIGITAL OUTPUTS Digital Output Buffers Figure 12 shows an equivalent circuit for a single output buffer. Each buffer is powered by OVDD and OGND, iso- lated from the ADC power and ground. The additional N-channel transistor in the output driver allows operation down to low voltages. The internal resistor in series with the output makes the output appear as 50Ω to external circuitry and may eliminate the need for external damping resistors. As with all high speed/high resolution converters, the digi- tal output loading can affect the performance. The digital outputs of the LTC2293/LTC2292/LTC2291 should drive a minimal capacitive load to avoid possible interaction Figure 11. Sinusoidal Single-Ended CLK Drive CLK 50Ω 0.1µF 0.1µF 4.7µF 1k 1k FERRITE BEAD CLEAN SUPPLY SINUSOIDAL CLOCK INPUT 229321 F11 NC7SVU04 LTC2293 LTC2292 LTC2291 |
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Similar Description - LTC2293 |
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