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M5M51016BTP-10VL-I Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor

Part No. M5M51016BTP-10VL-I
Description  1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
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Maker  MITSUBISHI [Mitsubishi Electric Semiconductor]
Homepage  http://www.mitsubishichips.com
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M5M51016BTP-10VL-I Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor

   
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MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M51016BTP,RT-10VL-I,
-10VLL-I
9 Jul ,1997
CS BC1 BC2 W
OE
Mode
Non selection
DQ1~8 DQ9~16
Stand-by
High-Z
ICC
L
X
X
X
X
High-Z
Non selection
Stand-by
High-Z
X
H
H
X
X
High-Z
Upper-Byte Write
Active
High-Z
H
H
L
L
X
Din
Upper-Byte Read
Active
High-Z
H
H
L
H
L
Dout
Active
High-Z
H
H
L
H
H
High-Z
Active
Din
H
L
H
L
X
High-Z
Active
Dout
H
L
H
H
L
High-Z
Lower-Byte Write
Lower-Byte Read
Active
High-Z
H
L
H
H
High-Z
H
Active
H
L
L
X
L
Din
Din
Word Write
Active
H
L
H
L
L
Dout
Dout
Word Read
Active
High-Z
H
L
H
H
High-Z
L
The operation mode of the M5M51016B series are determined by
a combination of the device control inputs BC1, BC 2, CS, W and
OE. Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level BC1 and/or BC2 and the high level CS. The address
must be set up before the write cycle and must be stable during
the entire cycle.
The data is latched into a cell on the trailing edge of W, BC1, BC2
or CS, whichever occurs first, requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the
databus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while BC1 and/or BC2 and CS are in an active state.
(BC1 and/or BC2=L,CS=H)
When setting BC1 at a high level and the other pins are in an
active state, upper-Byte are in a selectable mode in which both
reading and writing are enabled, and lower-Byte are in a
non-selectable mode.And when setting BC2 at a high level and the
other pins are in an active state, lower-Byte are in a selectable
mode and upper -Byte are in a non-selectable mode.
When setting BC1 and BC2 at a high level or CS at a low level,
the chips are in a non-selectable mode in which both reading and
writing are disabled.
In this mode, the output stage is in a high-impedance state,
allowing OR-tie with other chips and memory expansion by BC1,
BC2 and CS. The power supply current is reduced as low as the
stand-by current which is specified as ICC3 or ICC4, and the memory
data can be held at +2V power supply, enabling battery
back-up
operation during powerfailure or power-down operation in the
non-selected mode.
A1 9
A3 7
A6 4
A7 3
A12
A14 41
A1540
A13 39
A8 37
A0 10
A4 6
A2 8
A5 5
A9 36
A10 34
A11 35
11
43
42
38
13
CS
BC1
BC2
W
OE
15 DQ1
16 DQ2
17 DQ3
18 DQ4
19 DQ5
20 DQ6
21 DQ7
22 DQ8
24 DQ9
25 DQ10
26 DQ11
27 DQ12
28 DQ13
29 DQ14
30 DQ15
31 DQ16
CLOCK
GENERATOR
65536 WORDS x16 BITS
( 1024 ROWS
x 256 COLUMNS
x 4 BLOCKS )
ADDRESS
CHIP SELECT
INPUT
BYTE
CONTROL
INPUTS
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
23 Vcc
33 GND(0V)
12 GND (0V)
INPUTS
BLOCK DIAGRAM
2
FUNCTION
(High-Z=High-impedance)
2


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